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| author | Sudharsan Veeravalli <quic_svs@quicinc.com> | 2025-03-18 21:35:22 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-03-18 09:05:22 -0700 |
| commit | 467e5a1d41d63fd1c80fee14a8d99d32515c26d6 (patch) | |
| tree | ee740515d6f12d5388bb87b0ec4f6e71d8a60963 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | 4f7dc99a8a3e34e925ef66e7069b01b811e837ba (diff) | |
| download | llvm-467e5a1d41d63fd1c80fee14a8d99d32515c26d6.zip llvm-467e5a1d41d63fd1c80fee14a8d99d32515c26d6.tar.gz llvm-467e5a1d41d63fd1c80fee14a8d99d32515c26d6.tar.bz2 | |
[RISCV] Add Qualcomm uC Xqcisim (Simulation Hint) extension (#128833)
This extension adds 10 instructions that provide hints to the interface
simulation environment.
The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/
This patch adds assembler only support.
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index a5d4101..e3c4cc3 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -653,7 +653,8 @@ static constexpr FeatureBitset XqciFeatureGroup = { RISCV::FeatureVendorXqcics, RISCV::FeatureVendorXqcicsr, RISCV::FeatureVendorXqciint, RISCV::FeatureVendorXqcili, RISCV::FeatureVendorXqcilia, RISCV::FeatureVendorXqcilo, - RISCV::FeatureVendorXqcilsm, RISCV::FeatureVendorXqcisls, + RISCV::FeatureVendorXqcilsm, RISCV::FeatureVendorXqcisim, + RISCV::FeatureVendorXqcisls, }; static constexpr FeatureBitset XSfVectorGroup = { |