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| author | Jim Lin <jim@andestech.com> | 2025-07-07 13:01:22 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-07-07 13:01:22 +0800 |
| commit | 3f33e7ba5b08a97939280e539ad20a34d54b2719 (patch) | |
| tree | 8f2a8df7b9de1d7723d127be1a48232eb8b56873 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | 9d8a1bec2b55dfc21b84202bb0d1a4e04c8470e8 (diff) | |
| download | llvm-3f33e7ba5b08a97939280e539ad20a34d54b2719.zip llvm-3f33e7ba5b08a97939280e539ad20a34d54b2719.tar.gz llvm-3f33e7ba5b08a97939280e539ad20a34d54b2719.tar.bz2 | |
[RISCV] Add Andes XAndesVSIntLoad (Andes Vector INT4 Load) extension (#147005)
The spec can be found at:
https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release.
This patch only implements MC support for XAndesVSIntLoad.
---------
Co-authored-by: Lino Hsing-Yu Peng <linopeng@andestech.com>
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index aa45e7e..b723958 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -775,7 +775,8 @@ static constexpr FeatureBitset XTHeadGroup = { static constexpr FeatureBitset XAndesGroup = { RISCV::FeatureVendorXAndesPerf, RISCV::FeatureVendorXAndesVBFHCvt, - RISCV::FeatureVendorXAndesVPackFPH, RISCV::FeatureVendorXAndesVDot}; + RISCV::FeatureVendorXAndesVSIntLoad, RISCV::FeatureVendorXAndesVPackFPH, + RISCV::FeatureVendorXAndesVDot}; static constexpr DecoderListEntry DecoderList32[]{ // Vendor Extensions |