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author | quic_hchandel <quic_hchandel@quicinc.com> | 2025-03-22 07:57:07 +0530 |
---|---|---|
committer | GitHub <noreply@github.com> | 2025-03-22 07:57:07 +0530 |
commit | 3840f787a21a66686f5d8bf61877d41f3a65f205 (patch) | |
tree | 6f6c36a4ff551689be033f954f84451cb5a69224 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
parent | 17b5d6b2420ea3f1638b62a3b721c355be533dcd (diff) | |
download | llvm-3840f787a21a66686f5d8bf61877d41f3a65f205.zip llvm-3840f787a21a66686f5d8bf61877d41f3a65f205.tar.gz llvm-3840f787a21a66686f5d8bf61877d41f3a65f205.tar.bz2 |
[RISCV] Add Qualcomm uC Xqcisync (Sync Delay) extension (#132184)
This extension adds nine instructions, eight for non-memory-mapped
devices synchronization and delay instruction.
The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.7.0
This patch adds assembler only support.
Co-authored-by: Sudharsan Veeravalli <quic_svs@quicinc.com>
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
-rw-r--r-- | llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 26 |
1 files changed, 18 insertions, 8 deletions
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 5abf15a..93cbf66 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -370,6 +370,15 @@ static DecodeStatus decodeUImmPlus1OperandGE(MCInst &Inst, uint32_t Imm, return MCDisassembler::Success; } +static DecodeStatus decodeUImmSlistOperand(MCInst &Inst, uint32_t Imm, + int64_t Address, + const MCDisassembler *Decoder) { + assert(isUInt<3>(Imm) && "Invalid Slist immediate"); + const uint8_t Slist[] = {0, 1, 2, 4, 8, 16, 15, 31}; + Inst.addOperand(MCOperand::createImm(Slist[Imm])); + return MCDisassembler::Success; +} + static DecodeStatus decodeUImmLog2XLenOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder) { @@ -663,14 +672,15 @@ static constexpr FeatureBitset XRivosFeatureGroup = { }; static constexpr FeatureBitset XqciFeatureGroup = { - RISCV::FeatureVendorXqcia, RISCV::FeatureVendorXqciac, - RISCV::FeatureVendorXqcibi, RISCV::FeatureVendorXqcibm, - RISCV::FeatureVendorXqcicli, RISCV::FeatureVendorXqcicm, - RISCV::FeatureVendorXqcics, RISCV::FeatureVendorXqcicsr, - RISCV::FeatureVendorXqciint, RISCV::FeatureVendorXqcilb, - RISCV::FeatureVendorXqcili, RISCV::FeatureVendorXqcilia, - RISCV::FeatureVendorXqcilo, RISCV::FeatureVendorXqcilsm, - RISCV::FeatureVendorXqcisim, RISCV::FeatureVendorXqcisls, + RISCV::FeatureVendorXqcia, RISCV::FeatureVendorXqciac, + RISCV::FeatureVendorXqcibi, RISCV::FeatureVendorXqcibm, + RISCV::FeatureVendorXqcicli, RISCV::FeatureVendorXqcicm, + RISCV::FeatureVendorXqcics, RISCV::FeatureVendorXqcicsr, + RISCV::FeatureVendorXqciint, RISCV::FeatureVendorXqcilb, + RISCV::FeatureVendorXqcili, RISCV::FeatureVendorXqcilia, + RISCV::FeatureVendorXqcilo, RISCV::FeatureVendorXqcilsm, + RISCV::FeatureVendorXqcisim, RISCV::FeatureVendorXqcisls, + RISCV::FeatureVendorXqcisync, }; static constexpr FeatureBitset XSfVectorGroup = { |