diff options
| author | Boyao Wang <wangboyao@bytedance.com> | 2025-09-12 15:38:41 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-09-12 15:38:41 +0800 |
| commit | a7521a81c4b7aa135086488a566eab2dbc6b1326 (patch) | |
| tree | d40eeb63bff40d9e4c9920badcb8fdc9d5c7edfc /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | 152d0f5c0c0eaea369bf534b673d7625700ca7ef (diff) | |
| download | llvm-a7521a81c4b7aa135086488a566eab2dbc6b1326.zip llvm-a7521a81c4b7aa135086488a566eab2dbc6b1326.tar.gz llvm-a7521a81c4b7aa135086488a566eab2dbc6b1326.tar.bz2 | |
[RISCV][MC] Add MC support of Zibi experimental extension (#127463)
This adds the MC support of Zibi v0.1 experimental extension.
References:
*
https://lf-riscv.atlassian.net/wiki/spaces/USXX/pages/599261201/Branch+with+Immediate+Zibi+Ratification+Plan
* https://lf-riscv.atlassian.net/browse/RVS-3828
* https://github.com/riscv/zibi/releases/tag/v0.1.0
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 61b86ab..fb5a35d 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -491,6 +491,14 @@ static DecodeStatus decodeUImmPlus1Operand(MCInst &Inst, uint32_t Imm, return MCDisassembler::Success; } +static DecodeStatus decodeImmZibiOperand(MCInst &Inst, uint32_t Imm, + int64_t Address, + const MCDisassembler *Decoder) { + assert(isUInt<5>(Imm) && "Invalid immediate"); + Inst.addOperand(MCOperand::createImm(Imm ? Imm : -1LL)); + return MCDisassembler::Success; +} + template <unsigned N> static DecodeStatus decodeSImmOperand(MCInst &Inst, uint32_t Imm, int64_t Address, |