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2020-03-27Write execution logs to a named log file (#409)Rupert Swarbrick8-83/+152
This patch adds a --log argument to spike. If not given, the behaviour is unchanged: messages logging execution of instructions and (if commit logging is enabled) commits go to stderr. If --log=P is given, Spike now writes these messages to a log file at the path P. This is nice, because they are no longer tangled up with other errors and warnings. The code is mostly plumbing: passing a FILE* object through to the functions that were using stderr. I've written a simple "log_file_t" class, which opens a log file if necessary and yields it or stderr.
2020-03-24Allow PATH lookup for executing dtc (#432)綺麗な賢狼ホロ1-1/+1
2020-03-23Merge pull request #425 from chihminchao/rvv-fix-2020-03-17Andrew Waterman10-25/+33
Rvv fix 2020 03 17
2020-03-23rvv: restrict segment load register ruleChih-Min Chao4-3/+4
For unit-strided and stride segment load, mask register can't overlap destination register if masked ref: https://github.com/riscv/riscv-v-spec/pull/395 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-03-23rvv: fix WARL behavior for vxsat and vxrmChih-Min Chao1-2/+2
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-03-23rvv: fix vdiv corner caseChih-Min Chao2-2/+2
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-03-23rvv: sf: handle signaling NaN for fmax/fminChih-Min Chao1-10/+10
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-03-23commitlog: fix wrong dump when exception occursChih-Min Chao2-8/+15
1. store_fault_access reorder the log and slow_path code 2. misaligned_access reset the log buffer in the beginning rather at the end of execution to avoid that uncompleted execution status is brought to the next instruction Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-03-23Don't acquire load reservation in the event of a faultAndrew Waterman2-2/+4
I think this bug wasn't caught because OS code never steps over faulting LR instructions in practice. The exception is either fatal (in which case the point is moot) or the LR is re-executed (in which case the point is also moot). Resolves #431
2020-03-22Fix hard-coded path to DTC that breaks packaging (#428)Joel Sherrill2-15/+3
configure.ac included code which detects and inserted a full path to dtc. Unfortunately, when building with a packaging system, this path reflects the path under a staged building area. Also the inclusion of a full path breaks the use case where someone keeps two versions of dtc on their computer and sets their PATH to switch between them. spike will continue to use the one on their PATH when it was built rather than the intended one. Co-authored-by: Joel Sherrill <joel@rtems.org>
2020-03-20ebreak should write mtval with 0, not pcAndrew Waterman3-3/+3
Resolves #426 The relevant passage in the spec does not mention software breakpoints as one of the cases that cause mtval to be set to a nonzero value: https://github.com/riscv/riscv-isa-manual/blob/274893e2f0365f904829bbb60fd05cc01d2bfb11/src/machine.tex#L2202
2020-03-16fixed htif exception typo (#423)Dai chou1-1/+1
2020-03-12rvv: commitlog: fix vrgather_vv dump (#421)Chih-Min Chao1-4/+4
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-03-12Merge pull request #420 from chihminchao/rvv-fix-2020-03-11Andrew Waterman10-30/+35
Rvv fix 2020 03 11
2020-03-12rvv: commitlog: fix missing dump for some instructionsChih-Min Chao8-29/+32
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-03-12rvv: fix vfmv.s.f and vfmv.f.sChih-Min Chao2-1/+3
vfmv.s.f check valid vstart vfmv.f.s reset vstart in the end Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-03-10Merge pull request #417 from chihminchao/rvv-fix-2020-03-09Andrew Waterman7-355/+437
Rvv fix 2020 03 09
2020-03-09op: rvv: update encodingChih-Min Chao1-315/+372
change to 0ce3ec1 1. mstatus.vs is changed and it is 0.9 draft feature 2. opcodes are separated into difference files by extensions. The opcodes are not modifed but order are differenct. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-03-09commitlog: enhance vector dumpChih-Min Chao2-5/+17
1. don't duplicate vconfig for lmul >=2 case 2. add l# to show prenset vl value Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-03-09rvv: enhance --varch to parse string type optionsZhen Wei3-34/+46
To improve the readability of varch argument and future configuration, the format of options within varch are changed from "v128:e64:s512" to "vlen:128,elen:64,slen:512".
2020-03-09rvv: handle middle value of vslidedown.vxChih-Min Chao1-1/+1
The spec doesn't limit the range of middle value. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-03-09rvv: vstart must be 0 for reduction instructionsChih-Min Chao1-0/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-03-05Make debug printfs only show in debug builds. (#414)Andrew Waterman1-6/+6
2020-03-04Don't clobber trigger types when initializing stateAndrew Waterman1-1/+1
2020-02-28Merge branch 'rswarbrick-mcountinhibit'Andrew Waterman2-0/+3
2020-02-28Add do-nothing support for mcountinhibit CSRRupert Swarbrick2-0/+3
This CSR appeared in version 1.11 of the ISA and is described in the Volume II: Privileged Architecture manual. It's an optional register and should read as zero if not implemented, which is what this patch does.
2020-02-28Enable SOFTFLOAT_ROUND_ODD for vfncvt.rod.f.f.wAndrew Waterman1-0/+1
2020-02-27Merge pull request #405 from riscv/mstatus-sxl-uxlUdit Khanna1-7/+8
Check presence of [S|U] extension for mstatus.[sxl|uxl] read/write
2020-02-27Check presence of [S|U] extension for mstatus.[sxl|uxl] read/writeUdit Khanna1-7/+8
2020-02-27Merge pull request #406 from rswarbrick/cflagsAndrew Waterman6-24/+325
Allow overriding CFLAGS and similar when building
2020-02-27Allow overriding CFLAGS and similar when buildingRupert Swarbrick6-24/+325
Before this patch, I don't think it was possible to change (say) CFLAGS as part of running the make command. Nor did setting them when running configure do anything. Getting this right is a little fiddly: for example, see Automake's approach at [1] ("AM_CFLAGS" and friends). This patch adds an "mcppbs-" prefix, and sets things up properly for CFLAGS, CPPFLAGS, CXXFLAGS and LDFLAGS. Note that the bulk of the patch is either the auto-generated configure script or the ax_*.m4 files vendored in from the autoconf archive (needed to handle --export-dynamic correctly without trashing settings from the user running configure). What's supposed to happen is as follows: - Base compilation flags that should apply to everything (standard optimisation flags, warning flags etc.) are defined in Makefile.in. - When the user runs configure, they can set compilation flags on the command line. These end up as environment variables in the shell script. - Compilation flags that can only be decided when we run configure (this is currently just whether we support -Wl,--export-dynamic) are appended to the configure-time LDFLAGS environment variable. - At the end of the configure script, these environment variables are spliced into Makefile.in to fill out the corresponding @<varname>@ entries. - When running make, the user might again override compilation flags. These will get appended to the flags found so far. As a concrete example: mkdir build cd build ../configure CXXFLAGS='-O3' make CXXFLAGS='-O0' will result in c++ compile commands that look like this: g++ -MMD -MP \ -DPREFIX=\"/usr/local\" -Wall -Wno-unused -g -O2 -std=c++11 \ -O3 \ -O0 \ -I. -I.. -I../fesvr -I../riscv -I../dummy_rocc -I../softfloat \ -I../spike_main -fPIC -c ../fesvr/elfloader.cc (I've added some newlines to wrap the long line). Note that we have the base flags from Makefile.in (called $(default-CXXFLAGS) there) first. Then we have the -O3 from the configure command. Finally we have the -O0 from the Make command line. And I can finally run "make CXXFLAGS='-O0 -g3'". Phew! [1] https://www.gnu.org/software/automake/manual/html_node/Flag-Variables-Ordering.html
2020-02-21Allow debug accesses from MMUs not bound to processorsAndrew Waterman1-1/+1
2020-02-21Initialize some uninitialized stateAndrew Waterman2-1/+4
2020-02-20Disallow access to debug memory region unless in debug modeAndrew Waterman2-3/+31
... as recommended, but not required, by the spec.
2020-02-20Debug can actually start at 0x0 nowAndrew Waterman1-2/+1
38438778f0fc34df8cdf748cc9f35e1d15e0c8db fixed the bug. cc @timsifive
2020-02-20Merge pull request #403 from chihminchao/rvv-fix-2020-02-20Andrew Waterman6-10/+3
Rvv fix 2020 02 20
2020-02-20rvv: only check segment overlapping in index loadChih-Min Chao1-4/+2
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-02-20rvv: also relax vmerge_vim/vvm when lmul = 1Chih-Min Chao2-2/+0
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-02-20rvv: also relax lmul in vfwredumChih-Min Chao2-2/+0
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-02-20commitlog: print vsew in bitChih-Min Chao1-1/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-02-20rvv: don't zero vstart in the beginningChih-Min Chao1-1/+0
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-02-18widening reductions are legal when LMUL=8Andrew Waterman1-1/+0
cc @chihminchao @HanKuanChen
2020-02-18Vector stores don't care if rd overlaps v0 (#400)Andrew Waterman5-13/+20
Since vector stores read rd, rather than write rd, there is no overlap constraint.
2020-02-18Merge pull request #396 from chihminchao/rvv-fix-2020-02-14Andrew Waterman17-25/+31
Rvv fix 2020 02 14
2020-02-18commitlog: fix printf format warningChih-Min Chao1-1/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-02-18rvv: make variable name match its meaningChih-Min Chao4-4/+4
zimm5 for unsigned and zero-extended simm5 for signed and signed-extended It is unsigned arithmetics Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-02-18rvv: fix vmsleu/vmsgtu/vsaddu.vi operand signed extensionChih-Min Chao3-3/+3
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-02-17v[f]merge: allow v0 overlap if LMUL = 1Andrew Waterman2-2/+0
The VI_CHECK_SSS macro enforces the weaker constraint.
2020-02-17vadc/vsbc: allow v0 overlap if LMUL = 1Andrew Waterman1-2/+2
The spec says, "For vadc and vsbc, an illegal instruction exception is raised if the destination vector register is v0 and LMUL > 1." cc @chihminchao @HanKuanChen
2020-02-15Merge branch 'avpatel-real_time_clint_v1'Andrew Waterman5-8/+35
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