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| author | Andrew Waterman <andrew@sifive.com> | 2020-03-23 12:41:05 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2020-03-23 12:43:31 -0700 |
| commit | b4add16f4923a782f79b478d980791ec1d0bee06 (patch) | |
| tree | 64a5b3e10571346886796d9315c3e97453f2be99 | |
| parent | ff7d6954aba0f6616c12a8cf304f5f38a6d0df12 (diff) | |
| download | riscv-isa-sim-b4add16f4923a782f79b478d980791ec1d0bee06.zip riscv-isa-sim-b4add16f4923a782f79b478d980791ec1d0bee06.tar.gz riscv-isa-sim-b4add16f4923a782f79b478d980791ec1d0bee06.tar.bz2 | |
Don't acquire load reservation in the event of a fault
I think this bug wasn't caught because OS code never steps over faulting
LR instructions in practice. The exception is either fatal (in which case
the point is moot) or the LR is re-executed (in which case the point is
also moot).
Resolves #431
| -rw-r--r-- | riscv/insns/lr_d.h | 3 | ||||
| -rw-r--r-- | riscv/insns/lr_w.h | 3 |
2 files changed, 4 insertions, 2 deletions
diff --git a/riscv/insns/lr_d.h b/riscv/insns/lr_d.h index 52090c3..3f3521b 100644 --- a/riscv/insns/lr_d.h +++ b/riscv/insns/lr_d.h @@ -1,4 +1,5 @@ require_extension('A'); require_rv64; +auto res = MMU.load_int64(RS1); MMU.acquire_load_reservation(RS1); -WRITE_RD(MMU.load_int64(RS1)); +WRITE_RD(res); diff --git a/riscv/insns/lr_w.h b/riscv/insns/lr_w.h index c5845a6..8605cc5 100644 --- a/riscv/insns/lr_w.h +++ b/riscv/insns/lr_w.h @@ -1,3 +1,4 @@ require_extension('A'); +auto res = MMU.load_int32(RS1); MMU.acquire_load_reservation(RS1); -WRITE_RD(MMU.load_int32(RS1)); +WRITE_RD(res); |