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authorAndrew Waterman <andrew@sifive.com>2020-03-12 10:32:57 -0700
committerGitHub <noreply@github.com>2020-03-12 10:32:57 -0700
commitf048ad619f660762f9f4b5213b6914aef75db1a4 (patch)
treeb326da4766befec305c645860e32473c5c1339c8
parent4c9b5767414cd9e2603ec99de8e9b8b199b5a1db (diff)
parent5a22115f62bc9ee876e27679b54f02cc946e5cf7 (diff)
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Merge pull request #420 from chihminchao/rvv-fix-2020-03-11
Rvv fix 2020 03 11
-rw-r--r--riscv/decode.h8
-rw-r--r--riscv/insns/vfmv_f_s.h2
-rw-r--r--riscv/insns/vfmv_s_f.h2
-rw-r--r--riscv/insns/vmulhsu_vx.h8
-rw-r--r--riscv/insns/vmv_s_x.h8
-rw-r--r--riscv/insns/vmvnfr_v.h9
-rw-r--r--riscv/insns/vrgather_vi.h8
-rw-r--r--riscv/insns/vrgather_vx.h8
-rw-r--r--riscv/insns/vwmulsu_vv.h6
-rw-r--r--riscv/insns/vwmulsu_vx.h6
10 files changed, 35 insertions, 30 deletions
diff --git a/riscv/decode.h b/riscv/decode.h
index 73514dc..1794475 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -564,7 +564,7 @@ static inline bool is_overlapped(const int astart, const int asize,
uint64_t mmask = (UINT64_MAX << (64 - mlen)) >> (64 - mlen - mpos); \
uint64_t vs2 = P.VU.elt<uint64_t>(insn.rs2(), midx); \
uint64_t vs1 = P.VU.elt<uint64_t>(insn.rs1(), midx); \
- uint64_t &res = P.VU.elt<uint64_t>(insn.rd(), midx); \
+ uint64_t &res = P.VU.elt<uint64_t>(insn.rd(), midx, true); \
res = (res & ~mmask) | ((op) & (1ULL << mpos)); \
} \
P.VU.vstart = 0;
@@ -1133,19 +1133,19 @@ VI_LOOP_END
switch(P.VU.vsew) { \
case e8: { \
sign_d##16_t vd_w = P.VU.elt<sign_d##16_t>(rd_num, i); \
- P.VU.elt<uint16_t>(rd_num, i) = \
+ P.VU.elt<uint16_t>(rd_num, i, true) = \
op1((sign_1##16_t)(sign_1##8_t)var0 op0 (sign_2##16_t)(sign_2##8_t)var1) + var2; \
} \
break; \
case e16: { \
sign_d##32_t vd_w = P.VU.elt<sign_d##32_t>(rd_num, i); \
- P.VU.elt<uint32_t>(rd_num, i) = \
+ P.VU.elt<uint32_t>(rd_num, i, true) = \
op1((sign_1##32_t)(sign_1##16_t)var0 op0 (sign_2##32_t)(sign_2##16_t)var1) + var2; \
} \
break; \
default: { \
sign_d##64_t vd_w = P.VU.elt<sign_d##64_t>(rd_num, i); \
- P.VU.elt<uint64_t>(rd_num, i) = \
+ P.VU.elt<uint64_t>(rd_num, i, true) = \
op1((sign_1##64_t)(sign_1##32_t)var0 op0 (sign_2##64_t)(sign_2##32_t)var1) + var2; \
} \
break; \
diff --git a/riscv/insns/vfmv_f_s.h b/riscv/insns/vfmv_f_s.h
index dbfe8f9..586b80e 100644
--- a/riscv/insns/vfmv_f_s.h
+++ b/riscv/insns/vfmv_f_s.h
@@ -26,3 +26,5 @@ if (FLEN == 64) {
} else {
WRITE_FRD(f32(vs2_0));
}
+
+P.VU.vstart = 0;
diff --git a/riscv/insns/vfmv_s_f.h b/riscv/insns/vfmv_s_f.h
index 1f319b5..84c5a3f 100644
--- a/riscv/insns/vfmv_s_f.h
+++ b/riscv/insns/vfmv_s_f.h
@@ -5,7 +5,7 @@ require_extension('F');
require(P.VU.vsew >= e32 && P.VU.vsew <= 64);
reg_t vl = P.VU.vl;
-if (vl > 0) {
+if (vl > 0 && P.VU.vstart < vl) {
reg_t rd_num = insn.rd();
switch(P.VU.vsew) {
diff --git a/riscv/insns/vmulhsu_vx.h b/riscv/insns/vmulhsu_vx.h
index cb2db3d..b0699f6 100644
--- a/riscv/insns/vmulhsu_vx.h
+++ b/riscv/insns/vmulhsu_vx.h
@@ -3,7 +3,7 @@ VI_CHECK_SSS(false);
VI_LOOP_BASE
switch(sew) {
case e8: {
- auto &vd = P.VU.elt<int8_t>(rd_num, i);
+ auto &vd = P.VU.elt<int8_t>(rd_num, i, true);
auto vs2 = P.VU.elt<int8_t>(rs2_num, i);
uint8_t rs1 = RS1;
@@ -11,7 +11,7 @@ case e8: {
break;
}
case e16: {
- auto &vd = P.VU.elt<int16_t>(rd_num, i);
+ auto &vd = P.VU.elt<int16_t>(rd_num, i, true);
auto vs2 = P.VU.elt<int16_t>(rs2_num, i);
uint16_t rs1 = RS1;
@@ -19,7 +19,7 @@ case e16: {
break;
}
case e32: {
- auto &vd = P.VU.elt<int32_t>(rd_num, i);
+ auto &vd = P.VU.elt<int32_t>(rd_num, i, true);
auto vs2 = P.VU.elt<int32_t>(rs2_num, i);
uint32_t rs1 = RS1;
@@ -27,7 +27,7 @@ case e32: {
break;
}
default: {
- auto &vd = P.VU.elt<int64_t>(rd_num, i);
+ auto &vd = P.VU.elt<int64_t>(rd_num, i, true);
auto vs2 = P.VU.elt<int64_t>(rs2_num, i);
uint64_t rs1 = RS1;
diff --git a/riscv/insns/vmv_s_x.h b/riscv/insns/vmv_s_x.h
index 99db2a0..9964901 100644
--- a/riscv/insns/vmv_s_x.h
+++ b/riscv/insns/vmv_s_x.h
@@ -11,16 +11,16 @@ if (vl > 0 && P.VU.vstart < vl) {
switch(sew) {
case e8:
- P.VU.elt<uint8_t>(rd_num, 0) = RS1;
+ P.VU.elt<uint8_t>(rd_num, 0, true) = RS1;
break;
case e16:
- P.VU.elt<uint16_t>(rd_num, 0) = RS1;
+ P.VU.elt<uint16_t>(rd_num, 0, true) = RS1;
break;
case e32:
- P.VU.elt<uint32_t>(rd_num, 0) = RS1;
+ P.VU.elt<uint32_t>(rd_num, 0, true) = RS1;
break;
default:
- P.VU.elt<uint64_t>(rd_num, 0) = RS1;
+ P.VU.elt<uint64_t>(rd_num, 0, true) = RS1;
break;
}
diff --git a/riscv/insns/vmvnfr_v.h b/riscv/insns/vmvnfr_v.h
index 6ae66d5..bafcb4d 100644
--- a/riscv/insns/vmvnfr_v.h
+++ b/riscv/insns/vmvnfr_v.h
@@ -6,7 +6,10 @@ const reg_t vs2 = insn.rs2();
const reg_t len = insn.rs1() + 1;
require((vd & (len - 1)) == 0);
require((vs2 & (len - 1)) == 0);
-if (vd != vs2)
- memcpy(&P.VU.elt<uint8_t>(vd, 0),
- &P.VU.elt<uint8_t>(vs2, 0), P.VU.vlenb * len);
+if (vd != vs2) {
+ for (reg_t i = 0; i < len; ++i) {
+ memcpy(&P.VU.elt<uint8_t>(vd + i, 0, true),
+ &P.VU.elt<uint8_t>(vs2 + i, 0), P.VU.vlenb);
+ }
+}
P.VU.vstart = 0;
diff --git a/riscv/insns/vrgather_vi.h b/riscv/insns/vrgather_vi.h
index cab4a78..f63110e 100644
--- a/riscv/insns/vrgather_vi.h
+++ b/riscv/insns/vrgather_vi.h
@@ -14,16 +14,16 @@ for (reg_t i = P.VU.vstart; i < vl; ++i) {
switch (sew) {
case e8:
- P.VU.elt<uint8_t>(rd_num, i) = zimm5 >= P.VU.vlmax ? 0 : P.VU.elt<uint8_t>(rs2_num, zimm5);
+ P.VU.elt<uint8_t>(rd_num, i, true) = zimm5 >= P.VU.vlmax ? 0 : P.VU.elt<uint8_t>(rs2_num, zimm5);
break;
case e16:
- P.VU.elt<uint16_t>(rd_num, i) = zimm5 >= P.VU.vlmax ? 0 : P.VU.elt<uint16_t>(rs2_num, zimm5);
+ P.VU.elt<uint16_t>(rd_num, i, true) = zimm5 >= P.VU.vlmax ? 0 : P.VU.elt<uint16_t>(rs2_num, zimm5);
break;
case e32:
- P.VU.elt<uint32_t>(rd_num, i) = zimm5 >= P.VU.vlmax ? 0 : P.VU.elt<uint32_t>(rs2_num, zimm5);
+ P.VU.elt<uint32_t>(rd_num, i, true) = zimm5 >= P.VU.vlmax ? 0 : P.VU.elt<uint32_t>(rs2_num, zimm5);
break;
default:
- P.VU.elt<uint64_t>(rd_num, i) = zimm5 >= P.VU.vlmax ? 0 : P.VU.elt<uint64_t>(rs2_num, zimm5);
+ P.VU.elt<uint64_t>(rd_num, i, true) = zimm5 >= P.VU.vlmax ? 0 : P.VU.elt<uint64_t>(rs2_num, zimm5);
break;
}
}
diff --git a/riscv/insns/vrgather_vx.h b/riscv/insns/vrgather_vx.h
index 15e16b7..a91d58c 100644
--- a/riscv/insns/vrgather_vx.h
+++ b/riscv/insns/vrgather_vx.h
@@ -10,16 +10,16 @@ reg_t rs1 = RS1;
VI_LOOP_BASE
switch (sew) {
case e8:
- P.VU.elt<uint8_t>(rd_num, i) = rs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint8_t>(rs2_num, rs1);
+ P.VU.elt<uint8_t>(rd_num, i, true) = rs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint8_t>(rs2_num, rs1);
break;
case e16:
- P.VU.elt<uint16_t>(rd_num, i) = rs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint16_t>(rs2_num, rs1);
+ P.VU.elt<uint16_t>(rd_num, i, true) = rs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint16_t>(rs2_num, rs1);
break;
case e32:
- P.VU.elt<uint32_t>(rd_num, i) = rs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint32_t>(rs2_num, rs1);
+ P.VU.elt<uint32_t>(rd_num, i, true) = rs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint32_t>(rs2_num, rs1);
break;
default:
- P.VU.elt<uint64_t>(rd_num, i) = rs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint64_t>(rs2_num, rs1);
+ P.VU.elt<uint64_t>(rd_num, i, true) = rs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint64_t>(rs2_num, rs1);
break;
}
VI_LOOP_END;
diff --git a/riscv/insns/vwmulsu_vv.h b/riscv/insns/vwmulsu_vv.h
index 9786adb..5f84721 100644
--- a/riscv/insns/vwmulsu_vv.h
+++ b/riscv/insns/vwmulsu_vv.h
@@ -4,13 +4,13 @@ VI_VV_LOOP_WIDEN
({
switch(P.VU.vsew) {
case e8:
- P.VU.elt<uint16_t>(rd_num, i) = (int16_t)(int8_t)vs2 * (int16_t)(uint8_t)vs1;
+ P.VU.elt<uint16_t>(rd_num, i, true) = (int16_t)(int8_t)vs2 * (int16_t)(uint8_t)vs1;
break;
case e16:
- P.VU.elt<uint32_t>(rd_num, i) = (int32_t)(int16_t)vs2 * (int32_t)(uint16_t)vs1;
+ P.VU.elt<uint32_t>(rd_num, i, true) = (int32_t)(int16_t)vs2 * (int32_t)(uint16_t)vs1;
break;
default:
- P.VU.elt<uint64_t>(rd_num, i) = (int64_t)(int32_t)vs2 * (int64_t)(uint32_t)vs1;
+ P.VU.elt<uint64_t>(rd_num, i, true) = (int64_t)(int32_t)vs2 * (int64_t)(uint32_t)vs1;
break;
}
})
diff --git a/riscv/insns/vwmulsu_vx.h b/riscv/insns/vwmulsu_vx.h
index feb1fd1..68d6d27 100644
--- a/riscv/insns/vwmulsu_vx.h
+++ b/riscv/insns/vwmulsu_vx.h
@@ -4,13 +4,13 @@ VI_VX_LOOP_WIDEN
({
switch(P.VU.vsew) {
case e8:
- P.VU.elt<uint16_t>(rd_num, i) = (int16_t)(int8_t)vs2 * (int16_t)(uint8_t)rs1;
+ P.VU.elt<uint16_t>(rd_num, i, true) = (int16_t)(int8_t)vs2 * (int16_t)(uint8_t)rs1;
break;
case e16:
- P.VU.elt<uint32_t>(rd_num, i) = (int32_t)(int16_t)vs2 * (int32_t)(uint16_t)rs1;
+ P.VU.elt<uint32_t>(rd_num, i, true) = (int32_t)(int16_t)vs2 * (int32_t)(uint16_t)rs1;
break;
default:
- P.VU.elt<uint64_t>(rd_num, i) = (int64_t)(int32_t)vs2 * (int64_t)(uint32_t)rs1;
+ P.VU.elt<uint64_t>(rd_num, i, true) = (int64_t)(int32_t)vs2 * (int64_t)(uint32_t)rs1;
break;
}
})