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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-03-17 01:43:43 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-03-23 21:53:53 -0700 |
| commit | 570ed5c37b6b12e6c6c689036ccbec843cc352b0 (patch) | |
| tree | 93591c4b977b6ba716bf29c0c6b2697a9885cc31 | |
| parent | 8663f6494e61185a20df0e87c5f17898ab86e7d7 (diff) | |
| download | riscv-isa-sim-570ed5c37b6b12e6c6c689036ccbec843cc352b0.zip riscv-isa-sim-570ed5c37b6b12e6c6c689036ccbec843cc352b0.tar.gz riscv-isa-sim-570ed5c37b6b12e6c6c689036ccbec843cc352b0.tar.bz2 | |
rvv: fix vdiv corner case
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
| -rw-r--r-- | riscv/insns/vdiv_vv.h | 2 | ||||
| -rw-r--r-- | riscv/insns/vdiv_vx.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/riscv/insns/vdiv_vv.h b/riscv/insns/vdiv_vv.h index 67da162..0d4bd0d 100644 --- a/riscv/insns/vdiv_vv.h +++ b/riscv/insns/vdiv_vv.h @@ -3,7 +3,7 @@ VI_VV_LOOP ({ if (vs1 == 0) vd = -1; - else if (vs2 == -(1 << (sew - 1)) && vs1 == -1) + else if (vs2 == (INT64_MIN >> (64 - sew)) && vs1 == -1) vd = vs2; else vd = vs2 / vs1; diff --git a/riscv/insns/vdiv_vx.h b/riscv/insns/vdiv_vx.h index 1a152bd..4052952 100644 --- a/riscv/insns/vdiv_vx.h +++ b/riscv/insns/vdiv_vx.h @@ -3,7 +3,7 @@ VI_VX_LOOP ({ if(rs1 == 0) vd = -1; - else if(vs2 == -(1 << (sew - 1)) && rs1 == -1) + else if(vs2 == (INT64_MIN >> (64 - sew)) && rs1 == -1) vd = vs2; else vd = vs2 / rs1; |