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2020-03-23rvv: restrict segment load register ruleChih-Min Chao4-3/+4
2020-03-23rvv: fix WARL behavior for vxsat and vxrmChih-Min Chao1-2/+2
2020-03-23rvv: fix vdiv corner caseChih-Min Chao2-2/+2
2020-03-23rvv: sf: handle signaling NaN for fmax/fminChih-Min Chao1-10/+10
2020-03-23commitlog: fix wrong dump when exception occursChih-Min Chao2-8/+15
2020-03-23Don't acquire load reservation in the event of a faultAndrew Waterman2-2/+4
2020-03-22Fix hard-coded path to DTC that breaks packaging (#428)Joel Sherrill2-15/+3
2020-03-20ebreak should write mtval with 0, not pcAndrew Waterman3-3/+3
2020-03-16fixed htif exception typo (#423)Dai chou1-1/+1
2020-03-12rvv: commitlog: fix vrgather_vv dump (#421)Chih-Min Chao1-4/+4
2020-03-12Merge pull request #420 from chihminchao/rvv-fix-2020-03-11Andrew Waterman10-30/+35
2020-03-12rvv: commitlog: fix missing dump for some instructionsChih-Min Chao8-29/+32
2020-03-12rvv: fix vfmv.s.f and vfmv.f.sChih-Min Chao2-1/+3
2020-03-10Merge pull request #417 from chihminchao/rvv-fix-2020-03-09Andrew Waterman7-355/+437
2020-03-09op: rvv: update encodingChih-Min Chao1-315/+372
2020-03-09commitlog: enhance vector dumpChih-Min Chao2-5/+17
2020-03-09rvv: enhance --varch to parse string type optionsZhen Wei3-34/+46
2020-03-09rvv: handle middle value of vslidedown.vxChih-Min Chao1-1/+1
2020-03-09rvv: vstart must be 0 for reduction instructionsChih-Min Chao1-0/+1
2020-03-05Make debug printfs only show in debug builds. (#414)Andrew Waterman1-6/+6
2020-03-04Don't clobber trigger types when initializing stateAndrew Waterman1-1/+1
2020-02-28Merge branch 'rswarbrick-mcountinhibit'Andrew Waterman2-0/+3
2020-02-28Add do-nothing support for mcountinhibit CSRRupert Swarbrick2-0/+3
2020-02-28Enable SOFTFLOAT_ROUND_ODD for vfncvt.rod.f.f.wAndrew Waterman1-0/+1
2020-02-27Merge pull request #405 from riscv/mstatus-sxl-uxlUdit Khanna1-7/+8
2020-02-27Check presence of [S|U] extension for mstatus.[sxl|uxl] read/writeUdit Khanna1-7/+8
2020-02-27Merge pull request #406 from rswarbrick/cflagsAndrew Waterman6-24/+325
2020-02-27Allow overriding CFLAGS and similar when buildingRupert Swarbrick6-24/+325
2020-02-21Allow debug accesses from MMUs not bound to processorsAndrew Waterman1-1/+1
2020-02-21Initialize some uninitialized stateAndrew Waterman2-1/+4
2020-02-20Disallow access to debug memory region unless in debug modeAndrew Waterman2-3/+31
2020-02-20Debug can actually start at 0x0 nowAndrew Waterman1-2/+1
2020-02-20Merge pull request #403 from chihminchao/rvv-fix-2020-02-20Andrew Waterman6-10/+3
2020-02-20rvv: only check segment overlapping in index loadChih-Min Chao1-4/+2
2020-02-20rvv: also relax vmerge_vim/vvm when lmul = 1Chih-Min Chao2-2/+0
2020-02-20rvv: also relax lmul in vfwredumChih-Min Chao2-2/+0
2020-02-20commitlog: print vsew in bitChih-Min Chao1-1/+1
2020-02-20rvv: don't zero vstart in the beginningChih-Min Chao1-1/+0
2020-02-18widening reductions are legal when LMUL=8Andrew Waterman1-1/+0
2020-02-18Vector stores don't care if rd overlaps v0 (#400)Andrew Waterman5-13/+20
2020-02-18Merge pull request #396 from chihminchao/rvv-fix-2020-02-14Andrew Waterman17-25/+31
2020-02-18commitlog: fix printf format warningChih-Min Chao1-1/+1
2020-02-18rvv: make variable name match its meaningChih-Min Chao4-4/+4
2020-02-18rvv: fix vmsleu/vmsgtu/vsaddu.vi operand signed extensionChih-Min Chao3-3/+3
2020-02-17v[f]merge: allow v0 overlap if LMUL = 1Andrew Waterman2-2/+0
2020-02-17vadc/vsbc: allow v0 overlap if LMUL = 1Andrew Waterman1-2/+2
2020-02-15Merge branch 'avpatel-real_time_clint_v1'Andrew Waterman5-8/+35
2020-02-15Make CLINT API use Hz instead of MHzAndrew Waterman3-6/+6
2020-02-15Add optional support for real-time clintAnup Patel5-8/+35
2020-02-14rvv: fix exception rethrow in fault-first loadChih-Min Chao1-1/+1
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