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2019-07-11Fix support for 32-bit hosts (but no V extension in that case!)Andrew Waterman1-0/+3
2019-07-05Avoid static initializers for variable-length arraysAndrew Waterman1-2/+2
The subsequent for-loop provides sufficient initialization if we no longer conditionalize its execution on vl being nonzero. Resolves #307
2019-06-18rvv: add floating-point instructionsChih-Min Chao1-1/+264
based on v-spec 0.7.1, support sections: 14/15.3 ~ 15.4 element size: 32 Signed-off-by: Bruce Hoult <bruce@hoult.org> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> Signed-off-by: Dave Wen <dave.wen@sifive.com>
2019-06-18rvv: add load/store instructionsChih-Min Chao1-0/+151
based on v-spec 0.7.1, support section: 7 element size: 8/16/32/64 Signed-off-by: Bruce Hoult <bruce@hoult.org> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> Signed-off-by: Dave Wen <dave.wen@sifive.com> Signed-off-by: Zakk Chen <zakk.chen@sifive.com>
2019-06-18rvv: add integer/fixed-point/mask/reduction/permutation instructionsChih-Min Chao1-0/+1041
based on v-spec 0.7.1, support sections: 12/13/15.1 ~ 15.2/16/17 element size: 8/16/32/64 support ediv: 1 Signed-off-by: Bruce Hoult <bruce@hoult.org> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> Signed-off-by: Dave Wen <dave.wen@sifive.com>
2019-06-18rvv: add control instructions and system register accessChih-Min Chao1-0/+1
Signed-off-by: Bruce Hoult <bruce@hoult.org> Signed-off-by: Dave Wen <dave.wen@sifive.com> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-06-14rvv: disasm: add v-spec 0.7.1 supportChih-Min Chao1-0/+10
support most of vector instruction except for AMO extension Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-04-02Implement debug hasel support (#287)Tim Newsome1-0/+3
* Implement hasel/hawindow support. This should allow simultaneous resume and halt to work. * Fix anyrunning/anyhalted bits. * Add --without-hasel argument for testing. * Make halt/resume times more equal. Switching threads after every instruction executed in debug mode leads to a lot of extra instructions being executed on the "other" thread when both are really supposed to halt/resume near-simultaneously. Fixed that by adding wfi to debug_rom.S, and implementing it to switch to the other hart as well as check for JTAG input. When resuming, write the hart ID to the debug ROM so that the DM knows which hart actually resumed. (Before simultaneous resume it just assumed the current one.) Also got rid of resume symbol in debug_rom.S since it had no purpose. * Preserve Debug ROM entry points. * Make sure minstret is correct when wfi happens.
2018-08-23Fix several disassembler bugsAndrew Waterman1-0/+1
h/t Shane Lardinois
2018-04-30Only break out of the simulator loop on WFI, not on CSR writesAndrew Waterman1-0/+6
Breaking out of the loop on WFI was intended to let other threads run when the current thread has no work to do. There's no advantage to doing so on CSR writes, and the unintentional change in thread interleaving broke some test programs that relied on short timer periods.
2018-03-21Implement Hauser misa.C misalignment proposal (#187)Andrew Waterman1-1/+1
See https://github.com/riscv/riscv-isa-manual/commit/0472bcdd166f45712492829a250e228bb45fa5e7 - Reads of xEPC[1] are masked when RVC is disabled - Writes to MISA are suppressed if they would cause a misaligned fetch - Misaligned PCs no longer need to be checked upon fetch
2018-03-03Implement clearing-misa.C-while-PC-is-misaligned proposalAndrew Waterman1-3/+3
See https://github.com/riscv/riscv-isa-manual/pull/139 Not adopted yet, but I'm putting the implementation here for reference.
2017-10-20Fix commit-log for Q extension, and for RV32 (#143)Andrew Waterman1-2/+2
* Fix commit-log for Q extension, and for RV32 The number of nibbles printed out now depends upon XLEN or FLEN, as appropriate. * Factor out FLEN calculation
2017-09-28Implement Q extensionAndrew Waterman1-11/+32
2017-04-19Fix builds with "--enable-commitlog"Palmer Dabbelt1-1/+1
2017-04-18debug: Use Debug-Module specific constants instead of global defines.Megan Wachs1-13/+0
2017-04-18debug: Checkpoint which somewhat works with OpenOCD v13, but still has some ↵Megan Wachs1-8/+5
bugs.
2017-04-17debug: Move things around, but addresses now conflict with ROM.Megan Wachs1-8/+13
2017-04-17Merge remote-tracking branch 'origin/priv-1.10' into HEADMegan Wachs1-10/+31
2017-04-10Implement new FP encodingAndrew Waterman1-5/+21
https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/_r7hBlzsEd8/cWPyJKMzCQAJ
2017-03-27Set badaddr=0 on illegal instruction trapsAndrew Waterman1-3/+3
2017-03-23Require little-endian hostAndrew Waterman1-0/+4
2017-02-20serialize simulator on wfiAndrew Waterman1-2/+3
This improves simulator perf when a thread is idle, or waiting on HTIF.
2017-02-13Abstract register read mostly working.Tim Newsome1-3/+9
Fails with not supported for 128-bit. Fails with exception (on rv32) with 64-bit. Succeeds (on rv32) with 32-bit.
2017-02-10Entering debug mode now jumps to "dynamic rom"Tim Newsome1-10/+6
2016-06-01Move sethaltnot and cleardebint.Tim Newsome1-2/+2
Now it matches Krste's memory map.
2016-05-24Move cleardebint, per spec.Tim Newsome1-1/+1
2016-05-23Remove dependency on include file in my homedir.Tim Newsome1-5/+0
2016-05-23Software breakpoints sort of work.Tim Newsome1-6/+0
2016-05-23Exceptions in Debug Mode, stay in Debug Mode.Tim Newsome1-0/+1
Now things don't blow up when reading a non-existent CSR.
2016-05-23Have Debug memory kind of working again.Tim Newsome1-6/+6
Debug exception -> ROM -> RAM -> ROM, then something goes wrong.
2016-05-23Add debug_module bus device.Tim Newsome1-3/+6
This should replace the ROM hack I implemented earlier, but for now both exist together. Back to the point where gdb connects, core jumps to ROM->RAM->ROM.
2016-05-23Make sure to translate Debug RAM addresses also.Tim Newsome1-0/+3
2016-05-23Clean up how Debug ROM is included.Tim Newsome1-1/+1
I'm not thrilled about including a static copy in so many cc files, and making the compiler throw it out. But without really grokking the Makefile this is the best it's going to be.
2016-05-23Can jump to and execute Debug ROM.Tim Newsome1-2/+5
Connect with gdb, and the core will jump to Debug ROM and start executing it. Then it crashes when it jumps to 0x400 because Debug RAM isn't implemented (and doesn't live there anyway, for now).
2016-05-23When gdb connects, jump to Debug ROM and segfault.Tim Newsome1-1/+6
2016-05-23Gutting direct-access gdb.Tim Newsome1-0/+4
2016-05-23Add writing to DCSR, DPC, DSCRATCH.Tim Newsome1-0/+5
Make those 3 CSRs writable.
2016-05-21Some bugfixes for CSR reading and setting FS for fflags updates (#43)Andy Wright1-1/+4
* csrrc[i] and csrrs[i] don't write CSRs if rs/zimm == 0 * Dirty fp state when setting new fp exceptions * Set FS to dirty for all non-zero fflags writes.
2016-03-02Fix ERET serialization strategyAndrew Waterman1-3/+6
It was screwing up the commit log.
2016-03-02Serialize simulator on ERETAndrew Waterman1-0/+6
This guarantees interrupts will eventually be taken.
2016-03-02WIP on priv spec v1.9Andrew Waterman1-3/+2
2016-03-01Upgrade to latest SoftFloatAndrew Waterman1-0/+4
2015-11-12Generate device tree for target machineAndrew Waterman1-0/+1
2015-11-12Access FP regs through a macroAndrew Waterman1-5/+6
This makes it easier to hook into them.
2015-10-05more work towards RVC 1.8Andrew Waterman1-4/+3
2015-10-02work towards rvc 1.8Andrew Waterman1-0/+3
2015-09-08Improve instruction fetchAndrew Waterman1-0/+2
- Performance for variable-length instructions is much better - Refill is simpler and faster - Support for instructions with overlapping opcodes (e.g. C.ADD + C.JALR)
2015-09-04Move towards RVC v1.8Andrew Waterman1-22/+19
2015-05-31Add rest of RV32C instructionsAndrew Waterman1-0/+1
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