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author | Andrew Waterman <andrew@sifive.com> | 2017-04-10 17:35:24 -0700 |
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committer | Andrew Waterman <andrew@sifive.com> | 2017-04-10 17:35:24 -0700 |
commit | d6fce459767509249311a120fddb21c844dc9b2c (patch) | |
tree | b54272d8ce52f773b13dd33ae94d634538ec6599 /riscv/decode.h | |
parent | 5f494a22db29d69893db4b39f488cf67c0ac6437 (diff) | |
download | riscv-isa-sim-d6fce459767509249311a120fddb21c844dc9b2c.zip riscv-isa-sim-d6fce459767509249311a120fddb21c844dc9b2c.tar.gz riscv-isa-sim-d6fce459767509249311a120fddb21c844dc9b2c.tar.bz2 |
Implement new FP encoding
https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/_r7hBlzsEd8/cWPyJKMzCQAJ
Diffstat (limited to 'riscv/decode.h')
-rw-r--r-- | riscv/decode.h | 26 |
1 files changed, 21 insertions, 5 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index bec548a..c3487b1 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -17,11 +17,12 @@ #include "encoding.h" #include "config.h" #include "common.h" +#include "softfloat_types.h" +#include "specialize.h" #include <cinttypes> typedef int64_t sreg_t; typedef uint64_t reg_t; -typedef uint64_t freg_t; const int NXPR = 32; const int NFPR = 32; @@ -134,7 +135,7 @@ private: #ifndef RISCV_ENABLE_COMMITLOG # define WRITE_REG(reg, value) STATE.XPR.write(reg, value) -# define WRITE_FREG(reg, value) DO_WRITE_FREG(reg, value) +# define WRITE_FREG(reg, value) DO_WRITE_FREG(reg, freg(value)) #else # define WRITE_REG(reg, value) ({ \ reg_t wdata = (value); /* value may have side effects */ \ @@ -142,7 +143,7 @@ private: STATE.XPR.write(reg, wdata); \ }) # define WRITE_FREG(reg, value) ({ \ - freg_t wdata = (value); /* value may have side effects */ \ + freg_t wdata = freg(value); /* value may have side effects */ \ STATE.log_reg_write = (commit_log_reg_t){((reg) << 1) | 1, wdata}; \ DO_WRITE_FREG(reg, wdata); \ }) @@ -218,8 +219,23 @@ private: #define invalid_pc(pc) ((pc) & 1) /* Convenience wrappers to simplify softfloat code sequences */ -#define f32(x) ((float32_t){(uint32_t)x}) -#define f64(x) ((float64_t){(uint64_t)x}) +#define isBoxedF32(r) (((r) & 0xffffffff00000000) == 0xffffffff00000000) +#define unboxF32(r) (isBoxedF32(r) ? (r) : defaultNaNF32UI) +#define unboxF64(r) (r) +struct freg_t { uint64_t v; }; +inline float32_t f32(uint32_t v) { return { v }; } +inline float64_t f64(uint64_t v) { return { v }; } +inline float32_t f32(freg_t r) { return f32(unboxF32(r.v)); } +inline float64_t f64(freg_t r) { return f64(unboxF64(r.v)); } +inline freg_t freg(float32_t f) { return { ((decltype(freg_t::v))-1 << 32) | f.v }; } +inline freg_t freg(float64_t f) { return { f.v }; } +inline freg_t freg(freg_t f) { return f; } +#define F64_SIGN ((decltype(freg_t::v))1 << 63) +#define F32_SIGN ((decltype(freg_t::v))1 << 31) +#define fsgnj32(a, b, n, x) \ + f32((f32(a).v & ~F32_SIGN) | ((((x) ? f32(a).v : (n) ? F32_SIGN : 0) ^ f32(b).v) & F32_SIGN)) +#define fsgnj64(a, b, n, x) \ + f64((f64(a).v & ~F64_SIGN) | ((((x) ? f64(a).v : (n) ? F64_SIGN : 0) ^ f64(b).v) & F64_SIGN)) #define validate_csr(which, write) ({ \ if (!STATE.serialized) return PC_SERIALIZE_BEFORE; \ |