aboutsummaryrefslogtreecommitdiff
path: root/riscv/decode.h
AgeCommit message (Collapse)AuthorFilesLines
2024-04-18Add Zicfiss extension from CFI extension, v0.4.0SuHsien Ho1-0/+1
1. Add EXT_ZICFISS for enable Zicfiss with zicfiss extension name. 2. Add new software exception with tval 3 for shadow stack. 3. Implement sspush_x1/sspush_x5/sspopchk_x1/sspopchk_x5/ssrdp/ssamoswap_w/ssamoswap_d. 4. Implement c_sspush_x1/c_sspopchk_x5 in c_lui.h which has same encoding. 5. Add new special access type ss_access in xlate_flags_t for checking special read/write permission in SS(Shadow Stack) page. 6. Add new ss_load/ss_store/ssamoswap to enable ss_access flag. 7. Check special pte(xwr=010) of SS page.
2023-10-18Revert "tmp"Andrew Waterman1-1/+0
This reverts commit 1de1e81952e387ef6b282dc46f0fdf9ae4f74df5.
2023-10-18tmpAndrew Waterman1-0/+1
2023-06-19Zvk: Implement Zvbb, Vector Bit-manipulation for CryptographyEric Gouriou1-0/+1
Implement the proposed instructions in Zvbb: - vandn.{vv,vx}, vector bitwise and-not - vbrev.v, vector bit reverse in element - vbrev8.v, vector bit reverse in bytes - vrev8.v, vector byte reverse - vctz.v, vector count trailing zeros - vclz.v, vector count leading zeros - vcpop.v, vector population count - vrol.{vv,vx}, vector rotate left - vror.{vi,vv,vx}, vector rotate right - vwsll.{vi,vv,vx} vector widening shift left logical A new instruction field, 'zimm6', is introduced, encoded in bits [15, 19] and [26].. It is used by "vror.vi" to encode a shift immediate in [0, 63]. Co-authored-by: Raghav Gupta <rgupta@rivosinc.com> Co-authored-by: Stanislaw Kardach <kda@semihalf.com> Signed-off-by: Eric Gouriou <ego@rivosinc.com>
2023-05-26Use HAVE_INT128 instead of __SIZEOF_INT128__Gianluca Guida1-5/+0
Make sure that the configure decision on 128-bit is consistent during compilation. Also move uint128_t definition.
2023-02-21Update fields name for sreg1/sreg2Weiwei Li1-2/+2
2022-12-15Use relative include paths to support public usage of these headersJerry Zhao1-1/+1
2022-12-15Split decode.h into public decode.h and private decode_macros.hJerry Zhao1-310/+2
* decode.h contains constants/typedefs/classes. This should not depend on config.h * decode_macros.h contains internally used macros, and depends on config.h
2022-12-12Pull p/v_ext_macros.h out of decode.hJerry Zhao1-2/+0
2022-12-05Merge pull request #1162 from riscv-software-src/sfenceAndrew Waterman1-1/+3
SFENCE.W.INVAL and SFENCE.INVAL.IR should check privilege mode
2022-12-05SFENCE.INVAL.IR and SFENCE.W.INVAL are illegal in [V]U modesAndrew Waterman1-0/+2
See discussion on https://lists.riscv.org/g/tech-privileged/message/1213
2022-12-04Make require_novirt macro an expression, not a statementAndrew Waterman1-1/+1
This improves composability by allowing its use in other expressions.
2022-11-28Fix type error in some platformWeiwei Li1-1/+1
2022-11-17add support for zcmtWeiwei Li1-0/+2
add suport for jvt: Table entries follow the current data endianness
2022-11-17add support for zcmpWeiwei Li1-0/+75
2022-11-17add support for zcbWeiwei Li1-0/+3
2022-10-04Fix ignored-qualifiers warnings in get_field/set_field macrosAndrew Waterman1-2/+6
2022-10-04Rewrite READ_REG macro to avoid GNU statement expression extensionAndrew Waterman1-1/+1
This way, it can be used as an expression within a template argument.
2022-09-08Remove unnecessary argument alu(always false) from macroWeiwei Li1-3/+1
require_vector_novtype
2022-08-10Add space between if/while/switch and '('Weiwei Li1-3/+3
Add space between ')' and '{'
2022-08-04Add stateen related check for float point instructionsWeiwei Li1-1/+2
2022-08-04Modify F/D/Zfh instructions to add support for Zfinx/Zdinx/Zhinx{min} ↵liweiwei1-0/+42
instructions change the extention check for F/D/Zfh instructions modify the F/D/Zfh instructions to read X regs when enable Zfinx Co-authored-by: wangmeng <shusheng8495@hotmail.com>
2022-06-06Don't mask instruction bitsAndrew Waterman1-1/+1
No longer needed, since they are no longer sign-extended. Fixes #1022 by eliminating undefined behavior (64-bit instructions resulted in a shift amount equal to the datatype width).
2022-06-06insn_t: don't rely on sign-extension of internal encodingAndrew Waterman1-3/+3
2022-06-03Remove nonstandard length encoding (#1023)Andrew Waterman1-1/+0
This was an artifact of an old P-extension draft that erroneously allocated a reserved major opcode. The newer draft uses a different opcode, so this hack is no longer needed.
2022-06-01Remove the now-unused PC_SERIALIZE_WFIKip Walker1-2/+0
When WFI was changed to throw a C++ exception, the special-npc signaling became obsolete.
2022-05-05Factor out P extension macros into their own headerfactor-out-macrosAndrew Waterman1-500/+1
No functional change.
2022-05-05Factor out V extension macros into their own headerAndrew Waterman1-2069/+1
No functional change.
2022-04-14fix style problems in decode.h and processor.ccWeiwei Li1-266/+266
2022-04-09Replaced vector loop compare body with newly defined macro4vtomat1-90/+11
This commit uses new macro to replace loop compare body to enhance code reuse.
2022-04-09Adding new macro to replace repetitive code4vtomat1-0/+15
2022-02-23rvv: add missing elen checking for some ldst (#927)Chih-Min Chao1-0/+2
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2022-01-30add instructions function for cmoliweiwei1-0/+14
prefetch.* are hints and share the encoding of ORI with rd = 0. so it can share the implementation of ORI and execute as no-ops
2022-01-25Add more assertion for fcvt (#910)Yueh-Ting (eop) Chen1-0/+2
2022-01-10Merge pull request #899 from riscv-software-src/rv32eAndrew Waterman1-2/+4
Add RV32E/RV64E base ISA support
2022-01-09Changes to be cleaner wrt. -WextraAndrew Waterman1-1/+1
h/t @jerinjoy See #901
2022-01-06Support RV32E/RV64E base ISAsAndrew Waterman1-2/+4
2021-12-27Fix check for fcvt (#897)Yueh-Ting (eop) Chen1-9/+18
2021-12-23Fix check for fcvt (#894)Yueh-Ting (eop) Chen1-2/+2
2021-12-21Add missing check for floating-point merge instructions (#893)Yueh-Ting (eop) Chen1-4/+6
2021-12-17Merge pull request #881 from eopXD/simplify-float-convertAndrew Waterman1-30/+145
Simplify float convert instructions
2021-12-12Fix minor type-o (#885)Yueh-Ting (eop) Chen1-2/+2
2021-12-09Simplify vfwcvteopXD1-39/+50
2021-12-09Simplfy vfcvteopXD1-0/+34
2021-12-09Simplify vfncvteopXD1-0/+70
2021-12-07Merge pull request #879 from eopXD/simply-instsAndrew Waterman1-42/+124
Simply floating point parameters and merge operations
2021-12-07Simplify vadc and vsbc (#876)Yueh-Ting (eop) Chen1-6/+10
2021-12-07Merge pull request #868 from eopXD/simplify-narrowing-instAndrew Waterman1-47/+54
Simplify narrowing instruction
2021-12-08Simplify vmerge, vfmergeeopXD1-5/+66
2021-12-08Simplify floating point compare instructionseopXD1-13/+35
generated by cgit v1.1 at 2024-07-17 16:28:15 +0000