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| author | Tim Newsome <tim@sifive.com> | 2016-04-24 08:54:19 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2016-05-23 12:12:11 -0700 |
| commit | d999dfc0d41a119730ff8944d37dbee88bf99723 (patch) | |
| tree | 2268c9d7d5f122fb81253d10bd05901eaff0ff62 /riscv/decode.h | |
| parent | 191671a2015136c429394fd3051e4a9c1ff45352 (diff) | |
| download | riscv-isa-sim-d999dfc0d41a119730ff8944d37dbee88bf99723.zip riscv-isa-sim-d999dfc0d41a119730ff8944d37dbee88bf99723.tar.gz riscv-isa-sim-d999dfc0d41a119730ff8944d37dbee88bf99723.tar.bz2 | |
Add debug_module bus device.
This should replace the ROM hack I implemented earlier, but for now both
exist together.
Back to the point where gdb connects, core jumps to ROM->RAM->ROM.
Diffstat (limited to 'riscv/decode.h')
| -rw-r--r-- | riscv/decode.h | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 9b9df5b..5732a0d 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -14,7 +14,6 @@ #include "config.h" #include "common.h" #include <cinttypes> -#include "debug_rom/debug_rom.h" typedef int64_t sreg_t; typedef uint64_t reg_t; @@ -238,11 +237,15 @@ private: #define DCSR_CAUSE_HALT 5 #define DEBUG_START 0xfffffffffffff000 -#define DEBUG_RAM_START 0xfffffffffffffc00 // TODO: 0x400 -#define DEBUG_RAM_END (DEBUG_RAM_START + 64) #define DEBUG_ROM_START 0xfffffffffffff800 // TODO: 0x800 +#define DEBUG_ROM_RESUME (DEBUG_ROM_START + 4) #define DEBUG_ROM_END (DEBUG_ROM_START + debug_rom_raw_len) +#define DEBUG_RAM_START 0xfffffffffffffc00 // TODO: 0x400 +#define DEBUG_RAM_SIZE 64 +#define DEBUG_RAM_END (DEBUG_RAM_START + DEBUG_RAM_SIZE) #define DEBUG_END 0xffffffffffffffff +#define DEBUG_CLEARDEBINT 0xfffffffffffffef8 +#define DEBUG_SETHALTNOT 0xffffffffffffff00 #define DEBUG_SIZE (DEBUG_END - DEBUG_START + 1) #endif |