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| author | Tim Newsome <tim@sifive.com> | 2016-04-22 12:09:59 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2016-05-23 12:12:10 -0700 |
| commit | 576d311ad629914a7ef7cd0c6c22105329e3bb46 (patch) | |
| tree | 3e562777f2c3cd602ff029121051c53cfeff7fdf /riscv/decode.h | |
| parent | 5d1fb6b8c4eea6af9ebf02234724716ca25db3a1 (diff) | |
| download | riscv-isa-sim-576d311ad629914a7ef7cd0c6c22105329e3bb46.zip riscv-isa-sim-576d311ad629914a7ef7cd0c6c22105329e3bb46.tar.gz riscv-isa-sim-576d311ad629914a7ef7cd0c6c22105329e3bb46.tar.bz2 | |
Gutting direct-access gdb.
Diffstat (limited to 'riscv/decode.h')
| -rw-r--r-- | riscv/decode.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index b922e02..784c717 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -229,5 +229,9 @@ private: * automatically generated. */ /* TODO */ #include "/media/sf_tnewsome/Synced/SiFive/debug-spec/core_registers.tex.h" +#define DCSR_CAUSE_SWBP 1 +#define DCSR_CAUSE_HALT 5 + +#define DEBUG_ROM_ENTRY 0x800 #endif |