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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-03-01 16:24:05 -0800 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-03-01 16:24:44 -0800 |
| commit | a95b44df9d142a49f3e1bfe4a60d259ed41ca247 (patch) | |
| tree | 49f59c903609e5b0de05d5b0c7f7bd23de8c4f13 /riscv/decode.h | |
| parent | bea283531abfd013811e83c75ff6189a0d9b3075 (diff) | |
| download | riscv-isa-sim-a95b44df9d142a49f3e1bfe4a60d259ed41ca247.zip riscv-isa-sim-a95b44df9d142a49f3e1bfe4a60d259ed41ca247.tar.gz riscv-isa-sim-a95b44df9d142a49f3e1bfe4a60d259ed41ca247.tar.bz2 | |
Upgrade to latest SoftFloat
Diffstat (limited to 'riscv/decode.h')
| -rw-r--r-- | riscv/decode.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 5be6398..f525ff1 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -200,6 +200,10 @@ private: #define PC_SERIALIZE 3 /* sentinel value indicating simulator pipeline flush */ +/* Convenience wrappers to simplify softfloat code sequences */ +#define f32(x) ((float32_t){(uint32_t)x}) +#define f64(x) ((float64_t){(uint64_t)x}) + #define validate_csr(which, write) ({ \ if (!STATE.serialized) return PC_SERIALIZE; \ STATE.serialized = false; \ |