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author | Andrew Waterman <waterman@cs.berkeley.edu> | 2015-10-05 21:24:01 -0700 |
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committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2015-10-05 21:24:01 -0700 |
commit | b0f3ed6e3bc78f11371864a0587d918c547b8022 (patch) | |
tree | 099ef5a8fa6eec84fcdb5eac73c428c0294d5c93 /riscv/decode.h | |
parent | 3fddbcc0a5b2fc6a446967405e58a92be5db9f5f (diff) | |
download | riscv-isa-sim-b0f3ed6e3bc78f11371864a0587d918c547b8022.zip riscv-isa-sim-b0f3ed6e3bc78f11371864a0587d918c547b8022.tar.gz riscv-isa-sim-b0f3ed6e3bc78f11371864a0587d918c547b8022.tar.bz2 |
more work towards RVC 1.8
Diffstat (limited to 'riscv/decode.h')
-rw-r--r-- | riscv/decode.h | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 2e3e542..5cb4ed3 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -79,16 +79,15 @@ public: int64_t rvc_imm() { return x(2, 5) + (xs(12, 1) << 5); } int64_t rvc_zimm() { return x(2, 5) + (x(12, 1) << 5); } int64_t rvc_addi4spn_imm() { return (x(6, 1) << 2) + (x(5, 1) << 3) + (x(11, 2) << 4) + (x(7, 4) << 6); } - int64_t rvc_addi16sp_imm() { return (x(6, 1) << 4) + (x(5, 1) << 5) + (x(2, 3) << 6) + (xs(12, 1) << 9); } + int64_t rvc_addi16sp_imm() { return (x(6, 1) << 4) + (x(2, 1) << 5) + (x(5, 1) << 6) + (x(3, 2) << 7) + (xs(12, 1) << 9); } int64_t rvc_lwsp_imm() { return (x(4, 3) << 2) + (x(12, 1) << 5) + (x(2, 2) << 6); } int64_t rvc_ldsp_imm() { return (x(5, 2) << 3) + (x(12, 1) << 5) + (x(2, 3) << 6); } int64_t rvc_swsp_imm() { return (x(9, 4) << 2) + (x(7, 2) << 6); } int64_t rvc_sdsp_imm() { return (x(10, 3) << 3) + (x(7, 3) << 6); } int64_t rvc_lw_imm() { return (x(6, 1) << 2) + (x(10, 3) << 3) + (x(5, 1) << 6); } - int64_t rvc_lb_imm() { return (x(12, 1) + (x(5, 2) << 1) + (x(10, 2) << 3)); } int64_t rvc_ld_imm() { return (x(10, 3) << 3) + (x(5, 2) << 6); } - int64_t rvc_j_imm() { return (x(3, 4) << 1) + (x(2, 1) << 5) + (xs(7, 6) << 6); } - int64_t rvc_b_imm() { return (x(3, 4) << 1) + (x(2, 1) << 5) + (xs(10, 3) << 6); } + int64_t rvc_j_imm() { return (x(3, 3) << 1) + (x(11, 1) << 4) + (x(2, 1) << 5) + (x(7, 1) << 6) + (x(6, 1) << 7) + (x(9, 2) << 8) + (x(8, 1) << 10) + (xs(12, 1) << 11); } + int64_t rvc_b_imm() { return (x(3, 2) << 1) + (x(10, 2) << 3) + (x(2, 1) << 5) + (x(5, 2) << 6) + (xs(12, 1) << 8); } int64_t rvc_simm3() { return x(10, 3); } uint64_t rvc_rd() { return rd(); } uint64_t rvc_rs1() { return rd(); } |