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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2015-11-12 17:51:46 -0800 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2015-11-12 17:52:56 -0800 |
| commit | 0c3af3d73a28c0fc57eac535b2a28f45134b556b (patch) | |
| tree | a9ad7bab1842bde77d6755d96b22a45a510e7a41 /riscv/decode.h | |
| parent | a7bde15c2b79de12484748b462e511e0d1c2eca5 (diff) | |
| download | riscv-isa-sim-0c3af3d73a28c0fc57eac535b2a28f45134b556b.zip riscv-isa-sim-0c3af3d73a28c0fc57eac535b2a28f45134b556b.tar.gz riscv-isa-sim-0c3af3d73a28c0fc57eac535b2a28f45134b556b.tar.bz2 | |
Generate device tree for target machine
Diffstat (limited to 'riscv/decode.h')
| -rw-r--r-- | riscv/decode.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index a9713f4..5be6398 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -21,6 +21,7 @@ typedef uint64_t freg_t; const int NXPR = 32; const int NFPR = 32; +const int NCSR = 4096; #define X_RA 1 #define X_SP 2 |