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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-06-06 03:20:44 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-06-18 08:54:10 -0700 |
| commit | 235aa58bfb439c9782defe8bdd21f792e40aac31 (patch) | |
| tree | 3eec7c13834d660f47593c86e77e7f1281869165 /riscv/decode.h | |
| parent | 371e3fe5ef4017bececabe56e4958eb22ac0f08f (diff) | |
| download | riscv-isa-sim-235aa58bfb439c9782defe8bdd21f792e40aac31.zip riscv-isa-sim-235aa58bfb439c9782defe8bdd21f792e40aac31.tar.gz riscv-isa-sim-235aa58bfb439c9782defe8bdd21f792e40aac31.tar.bz2 | |
rvv: add control instructions and system register access
Signed-off-by: Bruce Hoult <bruce@hoult.org>
Signed-off-by: Dave Wen <dave.wen@sifive.com>
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/decode.h')
| -rw-r--r-- | riscv/decode.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 7ea1532..6cbf934 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -138,6 +138,7 @@ private: // helpful macros, etc #define MMU (*p->get_mmu()) #define STATE (*p->get_state()) +#define P (*p) #define READ_REG(reg) STATE.XPR[reg] #define READ_FREG(reg) STATE.FPR[reg] #define RS1 READ_REG(insn.rs1()) |