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| author | Tim Newsome <tim@sifive.com> | 2016-05-09 13:08:41 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2016-05-23 12:12:12 -0700 |
| commit | e67da00a3771a9487dad497580046d07884b893b (patch) | |
| tree | 3ee65e1bd4ed225ae6289e8eb5ce208ae10cdb81 /riscv/decode.h | |
| parent | 8b176c4e961c6eb376051a3db11078637f6bbffa (diff) | |
| download | riscv-isa-sim-e67da00a3771a9487dad497580046d07884b893b.zip riscv-isa-sim-e67da00a3771a9487dad497580046d07884b893b.tar.gz riscv-isa-sim-e67da00a3771a9487dad497580046d07884b893b.tar.bz2 | |
Remove dependency on include file in my homedir.
Diffstat (limited to 'riscv/decode.h')
| -rw-r--r-- | riscv/decode.h | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 1625398..f4c7640 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -225,11 +225,6 @@ private: throw trap_illegal_instruction(); \ (which); }) -/* Debug CSRs. These should probably be in encoding.h, but that file is - * automatically generated. */ -/* TODO */ -#include "/media/sf_tnewsome/Synced/SiFive/debug-spec/core_registers.tex.h" - #define DEBUG_START 0x100 #define DEBUG_ROM_START 0x800 #define DEBUG_ROM_RESUME (DEBUG_ROM_START + 4) |