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| author | Andrew Waterman <andrew@sifive.com> | 2017-02-20 18:48:35 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-02-20 18:48:35 -0800 |
| commit | 13639b9c457b3879efa620ce55abddbdc834ce68 (patch) | |
| tree | 4d8705117cf62d23067f042b663b5d020f8e6dbf /riscv/decode.h | |
| parent | b47e8c0a190ac17d2622d5554b21bc871d56847a (diff) | |
| download | riscv-isa-sim-13639b9c457b3879efa620ce55abddbdc834ce68.zip riscv-isa-sim-13639b9c457b3879efa620ce55abddbdc834ce68.tar.gz riscv-isa-sim-13639b9c457b3879efa620ce55abddbdc834ce68.tar.bz2 | |
serialize simulator on wfi
This improves simulator perf when a thread is idle, or waiting on HTIF.
Diffstat (limited to 'riscv/decode.h')
| -rw-r--r-- | riscv/decode.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index b607bf3..d82767d 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -202,9 +202,10 @@ private: } while(0) #define set_pc_and_serialize(x) \ - do { set_pc(x); /* check alignment */ \ + do { reg_t __npc = (x); \ + set_pc(__npc); /* check alignment */ \ npc = PC_SERIALIZE_AFTER; \ - STATE.pc = (x); \ + STATE.pc = __npc; \ } while(0) /* Sentinel PC values to serialize simulator pipeline */ |