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| author | Megan Wachs <megan@sifive.com> | 2017-04-17 19:28:49 -0700 |
|---|---|---|
| committer | Megan Wachs <megan@sifive.com> | 2017-04-17 19:28:49 -0700 |
| commit | 12b772563a33b6c6c3da0343fbfc747b1eeea6b6 (patch) | |
| tree | 35111fe1435f1b79f396955f2b9570b979b049cb /riscv/decode.h | |
| parent | 6480784223919308b347162e8589f79cffc4615e (diff) | |
| download | riscv-isa-sim-12b772563a33b6c6c3da0343fbfc747b1eeea6b6.zip riscv-isa-sim-12b772563a33b6c6c3da0343fbfc747b1eeea6b6.tar.gz riscv-isa-sim-12b772563a33b6c6c3da0343fbfc747b1eeea6b6.tar.bz2 | |
debug: Move things around, but addresses now conflict with ROM.
Diffstat (limited to 'riscv/decode.h')
| -rw-r--r-- | riscv/decode.h | 21 |
1 files changed, 13 insertions, 8 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 7667b27..551f451 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -246,19 +246,24 @@ inline freg_t freg(freg_t f) { return f; } throw trap_illegal_instruction(0); \ (which); }) -#define DEBUG_START 0x20000 -#define DEBUG_ROM_ENTRY DEBUG_START +// Seems that 0x0 doesn't work. +#define DEBUG_START 0x100 + +#define DEBUG_ROM_ENTRY 0x400 #define DEBUG_ROM_ENTRY_SIZE (1024 * 4) #define DEBUG_ROM_CODE (DEBUG_ROM_ENTRY + DEBUG_ROM_ENTRY_SIZE) #define DEBUG_ROM_CODE_SIZE 256 #define DEBUG_ROM_EXCEPTION (DEBUG_ROM_CODE + DEBUG_ROM_CODE_SIZE) #define DEBUG_ROM_EXCEPTION_SIZE 4 -#define DEBUG_RAM_START (DEBUG_ROM_EXCEPTION + DEBUG_ROM_EXCEPTION_SIZE) -#define DEBUG_RAM_SIZE 64 -#define DEBUG_RAM_END (DEBUG_RAM_START + DEBUG_RAM_SIZE) -#define DEBUG_END DEBUG_RAM_END -#define DEBUG_EXCHANGE 0x400 -#define DEBUG_EXCHANGE_SIZE 0x20 +#define DEBUG_DATA_START 0x380 +#define DEBUG_DATA_SIZE 0x20 +#define DEBUG_DATA_END DEBUG_DATA_START + DEBUG_DATA_SIZE + +#define DEBUG_PROGBUF_SIZE 32 +#define DEBUG_PROGBUF_START DEBUG_DATA_START - DEBUG_PROGBUF_SIZE +#define DEBUG_PROGBUF_END DEBUG_PROGBUF_START + DEBUG_PROGBUF_SIZE + +#define DEBUG_END 0x2000 - 1 #endif |