diff options
| author | Tim Newsome <tim@sifive.com> | 2016-04-30 15:24:38 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2016-05-23 12:12:11 -0700 |
| commit | 784fea2bbec803944eb923196c77d38427b3f554 (patch) | |
| tree | 273e526ac00c09b43c1e2b2986913503ccf1170b /riscv/decode.h | |
| parent | 47f64aaf95701d02a6b149b72422d319c8d99536 (diff) | |
| download | riscv-isa-sim-784fea2bbec803944eb923196c77d38427b3f554.zip riscv-isa-sim-784fea2bbec803944eb923196c77d38427b3f554.tar.gz riscv-isa-sim-784fea2bbec803944eb923196c77d38427b3f554.tar.bz2 | |
Exceptions in Debug Mode, stay in Debug Mode.
Now things don't blow up when reading a non-existent CSR.
Diffstat (limited to 'riscv/decode.h')
| -rw-r--r-- | riscv/decode.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 3a8b3a4..067d426 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -239,6 +239,7 @@ private: #define DEBUG_START 0x100 #define DEBUG_ROM_START 0x800 #define DEBUG_ROM_RESUME (DEBUG_ROM_START + 4) +#define DEBUG_ROM_EXCEPTION (DEBUG_ROM_START + 8) #define DEBUG_ROM_END (DEBUG_ROM_START + debug_rom_raw_len) #define DEBUG_RAM_START 0x400 #define DEBUG_RAM_SIZE 64 |