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| author | Andrew Waterman <andrew@sifive.com> | 2019-07-05 14:48:25 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-07-05 14:48:25 -0700 |
| commit | 6630944c5f5b938efdb88f4763ee3808e6c3b778 (patch) | |
| tree | 6897a0dd79890dc9a3d5ec78ab7fa70028b5ad07 /riscv/decode.h | |
| parent | 4290223cc68afdda5f6b9c83ffc8f291090c837e (diff) | |
| download | riscv-isa-sim-6630944c5f5b938efdb88f4763ee3808e6c3b778.zip riscv-isa-sim-6630944c5f5b938efdb88f4763ee3808e6c3b778.tar.gz riscv-isa-sim-6630944c5f5b938efdb88f4763ee3808e6c3b778.tar.bz2 | |
Avoid static initializers for variable-length arrays
The subsequent for-loop provides sufficient initialization if we no
longer conditionalize its execution on vl being nonzero.
Resolves #307
Diffstat (limited to 'riscv/decode.h')
| -rw-r--r-- | riscv/decode.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 1f80683..c588a86 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -1363,8 +1363,8 @@ VI_LOOP_END #define VI_DUPLICATE_VREG(v, vlmax) \ -reg_t index[vlmax] = {0}; \ -for (reg_t i = 0; i < vlmax && P.VU.vl != 0; ++i) { \ +reg_t index[vlmax]; \ +for (reg_t i = 0; i < vlmax; ++i) { \ switch(P.VU.vsew) { \ case e8: \ index[i] = P.VU.elt<int8_t>(v, i); \ |