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| author | Tim Newsome <tim@sifive.com> | 2016-04-22 15:10:23 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2016-05-23 12:12:10 -0700 |
| commit | d20be46eb4ffb94a9e7b2916dbc59a3666f21877 (patch) | |
| tree | 2afe7515cedd50d8fba20e4b8fbab74277c104ae /riscv/decode.h | |
| parent | ae566cba20a70f92c6cb778068e6e523602a2756 (diff) | |
| download | riscv-isa-sim-d20be46eb4ffb94a9e7b2916dbc59a3666f21877.zip riscv-isa-sim-d20be46eb4ffb94a9e7b2916dbc59a3666f21877.tar.gz riscv-isa-sim-d20be46eb4ffb94a9e7b2916dbc59a3666f21877.tar.bz2 | |
When gdb connects, jump to Debug ROM and segfault.
Diffstat (limited to 'riscv/decode.h')
| -rw-r--r-- | riscv/decode.h | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 784c717..d1254ee 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -229,9 +229,14 @@ private: * automatically generated. */ /* TODO */ #include "/media/sf_tnewsome/Synced/SiFive/debug-spec/core_registers.tex.h" +#define DCSR_CAUSE_NONE 0 #define DCSR_CAUSE_SWBP 1 +#define DCSR_CAUSE_HWBP 2 +#define DCSR_CAUSE_DEBUGINT 3 +#define DCSR_CAUSE_STEPPED 4 #define DCSR_CAUSE_HALT 5 -#define DEBUG_ROM_ENTRY 0x800 +#define DEBUG_RAM 0xfffffc00 // TODO: 0x400 +#define DEBUG_ROM_ENTRY 0xfffff800 // TODO: 0x800 #endif |