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| author | Tim Newsome <tim@sifive.com> | 2016-04-23 10:40:23 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2016-05-23 12:12:11 -0700 |
| commit | 78332ffbafeae5e9079bfc69ff136c5d24644a4c (patch) | |
| tree | 8bc0b585669a3c58e74d839fba2aeac9b813b3f4 /riscv/decode.h | |
| parent | df640b0cacf4ac6903b21c28e23fd9ef6861f94f (diff) | |
| download | riscv-isa-sim-78332ffbafeae5e9079bfc69ff136c5d24644a4c.zip riscv-isa-sim-78332ffbafeae5e9079bfc69ff136c5d24644a4c.tar.gz riscv-isa-sim-78332ffbafeae5e9079bfc69ff136c5d24644a4c.tar.bz2 | |
Make sure to translate Debug RAM addresses also.
Diffstat (limited to 'riscv/decode.h')
| -rw-r--r-- | riscv/decode.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index bf6a84c..9b9df5b 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -237,9 +237,12 @@ private: #define DCSR_CAUSE_STEPPED 4 #define DCSR_CAUSE_HALT 5 +#define DEBUG_START 0xfffffffffffff000 #define DEBUG_RAM_START 0xfffffffffffffc00 // TODO: 0x400 #define DEBUG_RAM_END (DEBUG_RAM_START + 64) #define DEBUG_ROM_START 0xfffffffffffff800 // TODO: 0x800 #define DEBUG_ROM_END (DEBUG_ROM_START + debug_rom_raw_len) +#define DEBUG_END 0xffffffffffffffff +#define DEBUG_SIZE (DEBUG_END - DEBUG_START + 1) #endif |