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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2015-09-08 15:09:23 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2015-09-08 17:00:02 -0700 |
| commit | 71d04ecd7ab631193a0943f8ddae222090d8e048 (patch) | |
| tree | 91a80a22da66a18d28bc79c39d26111e69fab26a /riscv/decode.h | |
| parent | 26d7f0f08e861335dc7bb2b51759c2206915a25a (diff) | |
| download | riscv-isa-sim-71d04ecd7ab631193a0943f8ddae222090d8e048.zip riscv-isa-sim-71d04ecd7ab631193a0943f8ddae222090d8e048.tar.gz riscv-isa-sim-71d04ecd7ab631193a0943f8ddae222090d8e048.tar.bz2 | |
Improve instruction fetch
- Performance for variable-length instructions is much better
- Refill is simpler and faster
- Support for instructions with overlapping opcodes (e.g. C.ADD + C.JALR)
Diffstat (limited to 'riscv/decode.h')
| -rw-r--r-- | riscv/decode.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 16e57d7..8462da2 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -53,6 +53,8 @@ const int NFPR = 32; ((x) & 0x1f) < 0x1f ? 4 : \ ((x) & 0x3f) < 0x3f ? 6 : \ 8) +#define MAX_INSN_LENGTH 8 +#define PC_ALIGN 2 typedef uint64_t insn_bits_t; class insn_t |