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| author | Tim Newsome <tim@sifive.com> | 2016-05-24 09:39:44 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2016-05-24 09:39:44 -0700 |
| commit | 8e11417db5e63af0abfb15915ba40f497cf8a646 (patch) | |
| tree | 6c95ae7d61163b3e4c5d847ab7adc392337c58e0 /riscv/decode.h | |
| parent | 4c3507d350460d4ce32621b8d6e77cd3cd93df7b (diff) | |
| download | riscv-isa-sim-8e11417db5e63af0abfb15915ba40f497cf8a646.zip riscv-isa-sim-8e11417db5e63af0abfb15915ba40f497cf8a646.tar.gz riscv-isa-sim-8e11417db5e63af0abfb15915ba40f497cf8a646.tar.bz2 | |
Move cleardebint, per spec.
Diffstat (limited to 'riscv/decode.h')
| -rw-r--r-- | riscv/decode.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index f4c7640..4480312 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -234,7 +234,7 @@ private: #define DEBUG_RAM_SIZE 64 #define DEBUG_RAM_END (DEBUG_RAM_START + DEBUG_RAM_SIZE) #define DEBUG_END 0xfff -#define DEBUG_CLEARDEBINT 0x108 +#define DEBUG_CLEARDEBINT 0x104 #define DEBUG_SETHALTNOT 0x100 #define DEBUG_SIZE (DEBUG_END - DEBUG_START + 1) |