| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2021-06-08 | Delete detailed text surrounding RVC immediates | Andrew Waterman | 1 | -4/+1 | |
| The metric is vague, and the only important point is the design pattern, not the exact cost. Resolves #659 | |||||
| 2021-05-25 | Use plural "base ISAs" rather than "base ISA" when appropriate | Andrew Waterman | 1 | -3/+3 | |
| cc @gfavor @kasanovic | |||||
| 2021-02-23 | s/NSE/Custom/ in RVC spec | Andrew Waterman | 1 | -1/+1 | |
| Resolves #629 | |||||
| 2021-01-13 | Revert "should -> shall in definition of 0 instruction" | Andrew Waterman | 1 | -1/+1 | |
| Didn't realize this was in non-normative text, where "shall" is pretty meaningless. This reverts commit c50f27ed34f3147fb0e3a7bc903ccd64ac02502f. | |||||
| 2021-01-13 | should -> shall in definition of 0 instruction | Andrew Waterman | 1 | -1/+1 | |
| 2020-08-23 | Clarify description of CB format | Andrew Waterman | 1 | -2/+2 | |
| Resolves #570 | |||||
| 2020-08-14 | Change "reserved for custom" to "designated for custom" (#566) | John Hauser | 1 | -5/+5 | |
| 2020-04-09 | Non misleading bit width expression in chapter C (#506) | Takahiro | 1 | -34/+34 | |
| 2019-10-02 | Weaken LR/SC progress guarantee | Andrew Waterman | 1 | -4/+4 | |
| 2019-06-26 | Clarify which hints are C.NOP hints and which are C.ADDI hints | Andrew Waterman | 1 | -4/+5 | |
| Closes #389 | |||||
| 2019-05-09 | Clarify reserved/HINT encodings in C chapter text (#382) | Andrew Waterman | 1 | -21/+54 | |
| This PR essentially copies the information from the encoding table at the end of the chapter into the mainline text. The intent is to remove any doubt about what happens when an instruction's operand constraints are not met. | |||||
| 2018-12-19 | Improve description of C opcode map | Andrew Waterman | 1 | -1/+3 | |
| 2018-12-19 | Improve rd'/rs1'/rs2' typesetting | Andrew Waterman | 1 | -78/+82 | |
| 2018-12-10 | subset -> extension | Andrew Waterman | 1 | -2/+2 | |
| 2018-11-16 | Change funct to funct2 in the CA format (#262) | Luís Marques | 1 | -2/+2 | |
| In the CA format, funct is changed to funct2, for consistency with the base ISA (which distinguishes between funct7 and funct3). | |||||
| 2018-11-06 | Define new RVC format CA; state that C.AND, etc. use it | Andrew Waterman | 1 | -6/+14 | |
| This is not a functional change, just an improvement to the description. Resolves #45 | |||||
| 2018-10-26 | A pair of somewhat pedantic changes to the wording of C.NOP (#248) | Palmer Dabbelt | 1 | -2/+2 | |
| * "c.addi x0, 0" isn't a legal instruction I was reviewing some QEMU patches recently and noticed an oddity of the current description of the ISA manual: the NOP instruction can also decode as a valid ADDI instruction, but the C.NOP instruction cannot decode as a valid C.ADDI instruction despite the ISA manual saying "C.NOP is encoded as c.addi x0, 0 and so expands to addi x0, x0, 0". This isn't a big deal, because "c.nop" does match what you'd expect the encoding of "c.addi x0, 0", but it is technically incorrect because the instruction "c.addi x0, 0" doesn't exist. This patch fixes the text of "c.nop" to just say it expands to "NOP". Signed-off-by: Palmer Dabbelt <palmer@sifive.com> * The performance counters must respect "c.nop" The non-compressed "nop" mentions that performance counters are modified by the instruction, but the text of the compressed instruction make it sound like that's not the case. | |||||
| 2018-08-30 | Remove text stating C.ADDI4SPN is RV32C/RV64C-only (#223) | Andrew | 1 | -3/+3 | |
| The paragraph of text describing C.ADDI4SPN states the instruction is RV32C/RV64C-only, but the opcode map indicates the instruction is available for RV128C too. This change updates the descriptive text, assuming that the opcode map is correct. | |||||
| 2018-07-16 | Updates to HINT sections. | Krste Asanovic | 1 | -4/+7 | |
| 2018-07-15 | More work on HINTs | Andrew Waterman | 1 | -15/+58 | |
| 2018-07-09 | Make JALR assembly format consistent with binutils (#209) | Andrew Waterman | 1 | -2/+2 | |
| Addresses #145 | |||||
| 2018-07-06 | C extension is no longer a draft proposal. | Krste Asanovic | 1 | -1/+1 | |
| Closed #73. | |||||
| 2018-06-16 | Fixed register name formatting error in c.tex. | Tynan McAuley | 1 | -1/+1 | |
| Changed the rs1-prime, rs2-prime, and rd-prime names to all be formatted as italics and to use the math-mode single quote, which is consistent with how these registers are formatted elsewhere in this file. | |||||
| 2018-05-30 | Hyphenate "instruction set" when it's part of a noun phrase | Andrew Waterman | 1 | -1/+1 | |
| 2018-05-04 | Revert "Fix inconsistency between RVC text and opcode table" | Andrew Waterman | 1 | -0/+3 | |
| This reverts commit 272d038abebe7f006ed7960b522f1e51890bb982. | |||||
| 2018-02-22 | Introduce IALIGN; propose misa.C semantics | Andrew Waterman | 1 | -3/+3 | |
| 2017-07-20 | Add note about C.MV | Andrew Waterman | 1 | -0/+7 | |
| 2017-05-20 | C.LUI uses nzimm, not nzuimm | Andrew Waterman | 1 | -2/+2 | |
| 2017-05-11 | Fix contradiction in C.ADDI definition | Andrew Waterman | 1 | -4/+5 | |
| It is a HINT when rd=0. | |||||
| 2017-05-07 | C -> 2.0 | Andrew Waterman | 1 | -7/+1 | |
| 2017-04-10 | Make immediate signs explicit in RVC table | Andrew Waterman | 1 | -4/+4 | |
| Adapted from @DSHorner's #31 | |||||
| 2017-03-10 | Fix quadrant for C.ADD/C.MV/C.EBREAK | Andrew Waterman | 1 | -3/+3 | |
| 2017-02-13 | Clarified instruction misaligned exceptions on JAL/JALR. | Krste Asanovic | 1 | -1/+5 | |
| 2017-02-01 | Reorganize directory structure | Andrew Waterman | 1 | -0/+1162 | |
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index : riscv-isa-manual.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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