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| author | Andrew Waterman <andrew@sifive.com> | 2021-01-13 18:00:13 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2021-01-13 18:00:13 -0800 |
| commit | ceabc373021840046e9918c6eb6a87ca3e15bd9b (patch) | |
| tree | fc42f586b176cf5bfdfba530cd3b6ed735f122b6 /src/c.tex | |
| parent | c50f27ed34f3147fb0e3a7bc903ccd64ac02502f (diff) | |
| download | riscv-isa-manual-ceabc373021840046e9918c6eb6a87ca3e15bd9b.zip riscv-isa-manual-ceabc373021840046e9918c6eb6a87ca3e15bd9b.tar.gz riscv-isa-manual-ceabc373021840046e9918c6eb6a87ca3e15bd9b.tar.bz2 | |
Revert "should -> shall in definition of 0 instruction"
Didn't realize this was in non-normative text, where "shall" is
pretty meaningless.
This reverts commit c50f27ed34f3147fb0e3a7bc903ccd64ac02502f.
Diffstat (limited to 'src/c.tex')
| -rw-r--r-- | src/c.tex | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -1114,7 +1114,7 @@ illegal instruction. \begin{commentary} We reserve all-zero instructions to be illegal instructions to help trap attempts to execute zero-ed or non-existent portions of the -memory space. The all-zero value shall not be redefined in any +memory space. The all-zero value should not be redefined in any non-standard extension. Similarly, we reserve instructions with all bits set to 1 (corresponding to very long instructions in the RISC-V variable-length encoding scheme) as illegal to capture another common |