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| author | Andrew Waterman <andrew@sifive.com> | 2018-12-10 12:21:03 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-12-10 12:21:03 -0800 |
| commit | bf33d5feb1290448e97fb5bf395c813923573068 (patch) | |
| tree | cc6ebfae4a89658b4270a0af7a9bf769673ad433 /src/c.tex | |
| parent | 42adb492c5b5b3913e20dc84111bc9be3391fb98 (diff) | |
| download | riscv-isa-manual-bf33d5feb1290448e97fb5bf395c813923573068.zip riscv-isa-manual-bf33d5feb1290448e97fb5bf395c813923573068.tar.gz riscv-isa-manual-bf33d5feb1290448e97fb5bf395c813923573068.tar.bz2 | |
subset -> extension
Diffstat (limited to 'src/c.tex')
| -rw-r--r-- | src/c.tex | 4 |
1 files changed, 2 insertions, 2 deletions
@@ -195,8 +195,8 @@ formats to allow access to all 32 data registers. CIW supplies an The RISC-V ABI was changed to make the frequently used registers map to registers {\tt x8}--{\tt x15}. This simplifies the decompression decoder by having a contiguous naturally aligned set of register -numbers, and is also compatible with the RV32E subset base -specification, which only has 16 integer registers. +numbers, and is also compatible with the RV32E base ISA, +which only has 16 integer registers. \end{commentary} Compressed register-based floating-point loads and stores also use the |