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| author | Andrew Waterman <andrew@sifive.com> | 2017-05-07 19:02:29 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-05-07 19:02:29 -0700 |
| commit | 650d64e15836ca556e90980115f27f44618b855b (patch) | |
| tree | a230293b690bef6566fef7457d76a156981e3582 /src/c.tex | |
| parent | b124462c76b2de6e61a3a752701f422b223b7322 (diff) | |
| download | riscv-isa-manual-650d64e15836ca556e90980115f27f44618b855b.zip riscv-isa-manual-650d64e15836ca556e90980115f27f44618b855b.tar.gz riscv-isa-manual-650d64e15836ca556e90980115f27f44618b855b.tar.bz2 | |
C -> 2.0
Diffstat (limited to 'src/c.tex')
| -rw-r--r-- | src/c.tex | 8 |
1 files changed, 1 insertions, 7 deletions
@@ -1,5 +1,5 @@ \chapter{``C'' Standard Extension for Compressed Instructions, Version -1.9} +2.0} \label{compressed} This chapter describes the current draft proposal for the RISC-V @@ -11,12 +11,6 @@ generic term ``RVC'' to cover any of these. Typically, 50\%--60\% of the RISC-V instructions in a program can be replaced with RVC instructions, resulting in a 25\%--30\% code-size reduction. -We believe this draft represents the close to final design for RV32C -and RV64C (it seems premature to freeze R128C), though we are -requesting one more round of comments, hence the 1.9 revision number. -Please send your comments to the {\tt isa-dev} mailing list at {\tt - isa-dev@lists.riscv.org}. - \section{Overview} RVC uses a simple compression scheme that offers shorter 16-bit |