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author | Andrew Waterman <andrew@sifive.com> | 2018-05-04 12:04:26 -0700 |
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committer | Andrew Waterman <andrew@sifive.com> | 2018-05-04 12:05:04 -0700 |
commit | 01190b6ebeb29cfac6783a3e7ce30cd529bf6c59 (patch) | |
tree | 0f4878b6ae7a4160e2b68ddd342ce5c717d56a28 /src/c.tex | |
parent | be663aebca2f8dd9572bf7071e2d721db729c1ba (diff) | |
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Revert "Fix inconsistency between RVC text and opcode table"
This reverts commit 272d038abebe7f006ed7960b522f1e51890bb982.
Diffstat (limited to 'src/c.tex')
-rw-r--r-- | src/c.tex | 3 |
1 files changed, 3 insertions, 0 deletions
@@ -389,16 +389,19 @@ These instructions use the CI format. C.LWSP loads a 32-bit value from memory into register {\em rd}. It computes an effective address by adding the {\em zero}-extended offset, scaled by 4, to the stack pointer, {\tt x2}. It expands to {\tt lw rd, offset[7:2](x2)}. +C.LWSP is only valid when $\textit{rd}{\neq}\texttt{x0}$. C.LDSP is an RV64C/RV128C-only instruction that loads a 64-bit value from memory into register {\em rd}. It computes its effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, {\tt x2}. It expands to {\tt ld rd, offset[8:3](x2)}. +C.LDSP is only valid when $\textit{rd}{\neq}\texttt{x0}$. C.LQSP is an RV128C-only instruction that loads a 128-bit value from memory into register {\em rd}. It computes its effective address by adding the zero-extended offset, scaled by 16, to the stack pointer, {\tt x2}. It expands to {\tt lq rd, offset[9:4](x2)}. +C.LQSP is only valid when $\textit{rd}{\neq}\texttt{x0}$. C.FLWSP is an RV32FC-only instruction that loads a single-precision floating-point value from memory into floating-point register {\em rd}. It |