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| author | Andrew Waterman <andrew@sifive.com> | 2021-02-23 16:47:47 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2021-02-23 16:48:05 -0800 |
| commit | 5ca937811c13ae142f783e69f61f6a402694ebe0 (patch) | |
| tree | 102f884fa48c867dd5b826a2699352e6eae9dc36 /src/c.tex | |
| parent | c879d5aaaaf6e8ba98dfa28376ae349ead8fa6c2 (diff) | |
| download | riscv-isa-manual-5ca937811c13ae142f783e69f61f6a402694ebe0.zip riscv-isa-manual-5ca937811c13ae142f783e69f61f6a402694ebe0.tar.gz riscv-isa-manual-5ca937811c13ae142f783e69f61f6a402694ebe0.tar.bz2 | |
s/NSE/Custom/ in RVC spec
Resolves #629
Diffstat (limited to 'src/c.tex')
| -rw-r--r-- | src/c.tex | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -1255,7 +1255,7 @@ least-significant bits set, corresponds to instructions wider than 16 bits, including those in the base ISAs. Several instructions are only valid for certain operands; when invalid, they are marked either {\em RES} to indicate that the opcode is reserved for future -standard extensions; {\em NSE} to indicate that the opcode is designated +standard extensions; {\em Custom} to indicate that the opcode is designated for custom extensions; or {\em HINT} to indicate that the opcode is reserved for microarchitectural hints (see Section~\ref{sec:rvc-hints}). |