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| author | Andrew Waterman <aswaterman@gmail.com> | 2018-07-09 15:51:54 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-07-09 15:51:54 -0700 |
| commit | 4dc3fa254ccc54e6f090722810506602ea59dbce (patch) | |
| tree | 9b36cdbca8ebfff093edb8d7087f34d3c196e4c8 /src/c.tex | |
| parent | 14257efc74521936c9d465a0aa6c22a2f419920e (diff) | |
| download | riscv-isa-manual-4dc3fa254ccc54e6f090722810506602ea59dbce.zip riscv-isa-manual-4dc3fa254ccc54e6f090722810506602ea59dbce.tar.gz riscv-isa-manual-4dc3fa254ccc54e6f090722810506602ea59dbce.tar.bz2 | |
Make JALR assembly format consistent with binutils (#209)
Addresses #145
Diffstat (limited to 'src/c.tex')
| -rw-r--r-- | src/c.tex | 4 |
1 files changed, 2 insertions, 2 deletions
@@ -673,12 +673,12 @@ C.JALR & src$\neq$0 & 0 & C2 \\ These instructions use the CR format. C.JR (jump register) performs an unconditional control transfer to -the address in register {\em rs1}. C.JR expands to {\tt jalr x0, rs1, 0}. +the address in register {\em rs1}. C.JR expands to {\tt jalr x0, 0(rs1)}. C.JALR (jump and link register) performs the same operation as C.JR, but additionally writes the address of the instruction following the jump ({\tt pc}+2) to the link register, {\tt x1}. C.JALR expands to -{\tt jalr x1, rs1, 0}. +{\tt jalr x1, 0(rs1)}. \begin{commentary} Strictly speaking, C.JALR does not expand exactly to a base RVI |