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| author | Andrew Waterman <andrew@sifive.com> | 2018-05-30 22:25:13 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-05-30 22:26:42 -0700 |
| commit | 40cf9350a6bf1c47d21a91fcdd1ba62a28731303 (patch) | |
| tree | 14484d7243dd344af851687d7fa9cd642b19ab54 /src/c.tex | |
| parent | d01dabf2c290dae77d12c8cfa288e6f9ac95cb55 (diff) | |
| download | riscv-isa-manual-40cf9350a6bf1c47d21a91fcdd1ba62a28731303.zip riscv-isa-manual-40cf9350a6bf1c47d21a91fcdd1ba62a28731303.tar.gz riscv-isa-manual-40cf9350a6bf1c47d21a91fcdd1ba62a28731303.tar.bz2 | |
Hyphenate "instruction set" when it's part of a noun phrase
Diffstat (limited to 'src/c.tex')
| -rw-r--r-- | src/c.tex | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -3,7 +3,7 @@ \label{compressed} This chapter describes the current draft proposal for the RISC-V -standard compressed instruction set extension, named ``C'', which +standard compressed instruction-set extension, named ``C'', which reduces static and dynamic code size by adding short 16-bit instruction encodings for common operations. The C extension can be added to any of the base ISAs (RV32, RV64, RV128), and we use the |