Change "reserved for custom" to "designated for custom" (#566)

1 files changed, 5 insertions, 5 deletions

diff --git a/src/c.tex b/src/c.tex
index 295a893..eda8367 100644
--- a/src/c.tex
+++ b/src/c.tex
@@ -895,7 +895,7 @@ C.SLLI expands into {\tt slli rd, rd, shamt}, except for
 RV128C with {\tt shamt=0}, which expands to {\tt slli rd, rd, 64}.
 
 For RV32C, {\em shamt[5]} must be zero; the code points with {\em shamt[5]}=1
-are reserved for custom extensions.  For RV32C and RV64C, the shift
+are designated for custom extensions.  For RV32C and RV64C, the shift
 amount must be non-zero; the code points with {\em shamt}=0 are HINTs.  For
 all base ISAs, the code points with {\em rd}={\tt x0} are HINTs, except those
 with {\em shamt[5]}=1 in RV32C.
@@ -935,7 +935,7 @@ except for RV128C with {\tt shamt=0}, which expands to
 {\tt srli \rdprime, \rdprime, 64}.
 
 For RV32C, {\em shamt[5]} must be zero; the code points with {\em shamt[5]}=1
-are reserved for custom extensions.  For RV32C and RV64C, the shift
+are designated for custom extensions.  For RV32C and RV64C, the shift
 amount must be non-zero; the code points with {\em shamt}=0 are HINTs.
 
 C.SRAI is defined analogously to C.SRLI, but instead performs an arithmetic
@@ -1219,7 +1219,7 @@ amenable to macro-op fusion.
 
 Table~\ref{tab:rvc-hints} lists all RVC HINT code points.  For RV32C, 78\% of
 the HINT space is reserved for standard HINTs, but none are presently defined.
-The remainder of the HINT space is reserved for custom HINTs: no standard
+The remainder of the HINT space is designated for custom HINTs; no standard
 HINTs will ever be defined in this subspace.
 
 \begin{table}[hbt]
@@ -1233,7 +1233,7 @@ HINTs will ever be defined in this subspace.
   C.LUI                   & {\em rd}={\tt x0}, {\em nzimm}$\neq$0       & 63          & \\ \cline{1-3}
   C.MV                    & {\em rd}={\tt x0}, {\em rs2}$\neq${\tt x0}  & 31          & \\ \cline{1-3}
   C.ADD                   & {\em rd}={\tt x0}, {\em rs2}$\neq${\tt x0}  & 31          & \\ \hline \hline
-  \multirow{2}{*}{C.SLLI} & \multirow{2}{*}{{\em rd}={\tt x0}, {\em nzimm}$\neq$0} & 31 (RV32)   & \multirow{6}{*}{\em Reserved for custom use} \\
+  \multirow{2}{*}{C.SLLI} & \multirow{2}{*}{{\em rd}={\tt x0}, {\em nzimm}$\neq$0} & 31 (RV32)   & \multirow{6}{*}{\em Designated for custom use} \\
                           &                                             & 63 (RV64/128) & \\ \cline{1-3}
   C.SLLI64                & {\em rd}={\tt x0}                           & 1           & \\ \cline{1-3}
   C.SLLI64                & {\em rd}$\neq${\tt x0}, RV32 and RV64 only  & 31          & \\ \cline{1-3}
@@ -1255,7 +1255,7 @@ least-significant bits set, corresponds to instructions wider
 than 16 bits, including those in the base ISAs.  Several instructions
 are only valid for certain operands; when invalid, they are marked
 either {\em RES} to indicate that the opcode is reserved for future
-standard extensions; {\em NSE} to indicate that the opcode is reserved
+standard extensions; {\em NSE} to indicate that the opcode is designated
 for custom extensions; or {\em HINT} to indicate that the opcode
 is reserved for microarchitectural hints (see Section~\ref{sec:rvc-hints}).