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| author | Andrew Waterman <andrew@sifive.com> | 2018-02-22 01:20:51 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-02-22 01:39:52 -0800 |
| commit | a4ade78dcbb56a84d6577b167443fbca3bf82770 (patch) | |
| tree | 2a5d5a5c517c6a0bbc4744f607a4fe50c8c22a1e /src/c.tex | |
| parent | a439dada57fe6c1ed426351742a5ba7dd2cace37 (diff) | |
| download | riscv-isa-manual-a4ade78dcbb56a84d6577b167443fbca3bf82770.zip riscv-isa-manual-a4ade78dcbb56a84d6577b167443fbca3bf82770.tar.gz riscv-isa-manual-a4ade78dcbb56a84d6577b167443fbca3bf82770.tar.bz2 | |
Introduce IALIGN; propose misa.C semantics
Diffstat (limited to 'src/c.tex')
| -rw-r--r-- | src/c.tex | 6 |
1 files changed, 3 insertions, 3 deletions
@@ -28,9 +28,9 @@ versions of common 32-bit RISC-V instructions when: The C extension is compatible with all other standard instruction extensions. The C extension allows 16-bit instructions to be freely intermixed with 32-bit instructions, with the latter now able to start -on any 16-bit boundary. With the addition of the C extension, JAL and -JALR instructions will no longer raise an instruction misaligned -exception. +on any 16-bit boundary, i.e., IALIGN=16. With the addition of the C +extension, no instructions can raise instruction-address-misaligned +exceptions. \pagebreak |