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author | Andrew Waterman <andrew@sifive.com> | 2019-06-26 14:07:27 -0700 |
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committer | Andrew Waterman <andrew@sifive.com> | 2019-06-26 14:07:47 -0700 |
commit | 9f0e2341734fb3dcbcec737fd21ff8d5f4e6ea00 (patch) | |
tree | 1ca3470c3fd1817633044ce0934429c842d1ada5 /src/c.tex | |
parent | 45e4d2b2ff866d8fccc27e4d441db5677111b733 (diff) | |
download | riscv-isa-manual-9f0e2341734fb3dcbcec737fd21ff8d5f4e6ea00.zip riscv-isa-manual-9f0e2341734fb3dcbcec737fd21ff8d5f4e6ea00.tar.gz riscv-isa-manual-9f0e2341734fb3dcbcec737fd21ff8d5f4e6ea00.tar.bz2 |
Clarify which hints are C.NOP hints and which are C.ADDI hints
Closes #389
Diffstat (limited to 'src/c.tex')
-rw-r--r-- | src/c.tex | 9 |
1 files changed, 5 insertions, 4 deletions
@@ -815,9 +815,9 @@ C.ADDI16SP & nzimm[9] & 2 & nzimm[4$\vert$6$\vert$8:7$\vert$5] & C1 \\ C.ADDI adds the non-zero sign-extended 6-bit immediate to the value in register {\em rd} then writes the result to {\em rd}. C.ADDI expands into {\tt addi rd, rd, nzimm[5:0]}. -C.ADDI is only valid when {\em rd}$\neq${\tt x0}. -The code point with both {\em rd}={\tt x0} and {\em nzimm}=0 encodes the C.NOP instruction; -the remaining code points with either {\em rd}={\tt x0} or {\em nzimm}=0 encode HINTs. +C.ADDI is only valid when {\em rd}$\neq${\tt x0} and {\em nzimm}$\neq$0. +The code points with {\em rd}={\tt x0} encode the C.NOP instruction; +the remaining code points with {\em nzimm}=0 encode HINTs. C.ADDIW is an RV64C/RV128C-only instruction that performs the same computation but produces a 32-bit result, then sign-extends result to @@ -1145,7 +1145,8 @@ C.NOP & 0 & 0 & 0 & C1 \\ C.NOP is a CI-format instruction that does not change any user-visible state, except for advancing the {\tt pc} and incrementing any applicable performance -counters. C.NOP expands to {\tt nop}. +counters. C.NOP expands to {\tt nop}. C.NOP is only valid when {\em imm}=0; +the code points with {\em imm}$\neq$0 encode HINTs. \subsection*{Breakpoint Instruction} \vspace{-0.4in} |