More work on HINTs

1 files changed, 58 insertions, 15 deletions

diff --git a/src/c.tex b/src/c.tex
index 0b47699..dcb22c3 100644
--- a/src/c.tex
+++ b/src/c.tex
@@ -1138,6 +1138,63 @@ the A and C extensions must ensure that LR/SC sequences containing
 valid C instructions will eventually complete.
 \end{commentary}
 
+\section{HINT Instructions}
+\label{sec:rvc-hints}
+
+A portion of the RVC encoding space is reserved for microarchitectural HINTs.
+Like the HINTs in the RV32I base ISA (see Section~\ref{sec:rv32i-hints}),
+these instructions do not modify any architectural state, except for advancing
+the {\tt pc} and the instructions-retired counter {\tt instret}.  HINTs are
+executed as no-ops on implementations that ignore them.
+
+RVC HINTs are encoded as computational instructions that do not modify the
+architectural state, either because {\em rd}={\tt x0}
+(e.g. \mbox{C.ADD {\em x0}, {\em t0}}), or because {\em rd} is overwritten
+with a copy of itself (e.g. \mbox{C.ADDI {\em t0}, 0}).
+
+\begin{commentary}
+This HINT encoding has been chosen so that simple implementations can ignore
+HINTs altogether, and instead execute a HINT as a regular computational
+instruction that happens not to mutate the architectural state.
+\end{commentary}
+
+RVC HINTs do not necessarily expand to their RVI HINT counterparts.  For
+example, \mbox{C.ADD {\em x0}, {\em t0}} might not encode the same HINT
+as \mbox{ADD {\em x0}, {\em x0}, {\em t0}}.
+
+\begin{commentary}
+We expect the static and dynamic frequency of HINT code points will vary
+dramatically.  Decoupling the RVC and RVI HINT mappings allows the scarce RVC
+HINT space to be allocated to the most popular HINTs.
+\end{commentary}
+
+Table~\ref{tab:rvc-hints} lists all RVC HINT code points.  For RV32C, 78\% of
+the HINT space is reserved for standard HINTs, but none are presently defined.
+The remainder of the HINT space is reserved for custom HINTs: no standard
+HINTs will ever be defined in this subspace.
+
+\begin{table}[hbt]
+\centering
+\begin{tabular}{|l|l|r|l|}
+  \hline
+  Instruction             & Constraints                                 & Code Points & Purpose \\ \hline \hline
+  C.NOP                   & {\em nzimm}$\neq$0                          & 63          & \multirow{6}{*}{\em Reserved for future standard use} \\ \cline{1-3}
+  C.ADDI                  & {\em rd}$\neq${\tt x0}, {\em nzimm}=0       & 31          & \\ \cline{1-3}
+  C.LI                    & {\em rd}={\tt x0}                           & 64          & \\ \cline{1-3}
+  C.LUI                   & {\em rd}={\tt x0}, {\em nzimm}$\neq$0       & 63          & \\ \cline{1-3}
+  C.MV                    & {\em rd}={\tt x0}, {\em rs2}$\neq${\tt x0}  & 31          & \\ \cline{1-3}
+  C.ADD                   & {\em rd}={\tt x0}, {\em rs2}$\neq${\tt x0}  & 31          & \\ \hline \hline
+  \multirow{2}{*}{C.SLLI} & \multirow{2}{*}{{\em rd}={\tt x0}, {\em nzimm}$\neq$0} & 31 (RV32)   & \multirow{6}{*}{\em Reserved for custom use} \\
+                          &                                             & 63 (RV64/128) & \\ \cline{1-3}
+  C.SLLI64                & {\em rd}={\tt x0}                           & 1           & \\ \cline{1-3}
+  C.SLLI64                & {\em rd}$\neq${\tt x0}, RV32 and RV64 only  & 31          & \\ \cline{1-3}
+  C.SRLI64                & RV32 and RV64 only                          & 8           & \\ \cline{1-3}
+  C.SRAI64                & RV32 and RV64 only                          & 8           & \\ \hline
+\end{tabular}
+\caption{RVC HINT instructions.}
+\label{tab:rvc-hints}
+\end{table}
+
 \clearpage
 
 \section{RVC Instruction Set Listings}
@@ -1149,21 +1206,7 @@ are only valid for certain operands; when invalid, they are marked
 either {\em RES} to indicate that the opcode is reserved for future
 standard extensions; {\em NSE} to indicate that the opcode is reserved
 for non-standard extensions; or {\em HINT} to indicate that the opcode
-is reserved for future standard microarchitectural hints.
-Instructions marked {\em HINT} must execute as no-ops on
-implementations for which the hint has no effect.
-
-\begin{commentary}
-The HINT instructions are designed to support future addition of
-microarchitectural hints that might affect performance but cannot
-affect architectural state.  The HINT encodings have been chosen so
-that simple implementations can ignore the HINT encoding and execute
-the HINT as a regular operation that does not change architectural
-state.  For example, C.ADD is a HINT if the destination register is
-{\tt x0}, where the five-bit rs2 field encodes details of the HINT.
-However, a simple implementation can simply execute the HINT as an add
-to register {\tt x0}, which will have no effect.
-\end{commentary}
+is reserved for microarchitectural hints (see Section~\ref{sec:rvc-hints}).
 
 \input{rvc-opcode-map}