Define new RVC format CA; state that C.AND, etc. use it

This is not a functional change, just an improvement to the description.

Resolves #45

1 files changed, 14 insertions, 6 deletions

diff --git a/src/c.tex b/src/c.tex
index 1a308d2..fbfcfa4 100644
--- a/src/c.tex
+++ b/src/c.tex
@@ -180,9 +180,9 @@ doubling the instruction cache size~\cite{waterman-ms}.
 
 \section{Compressed Instruction Formats}
 
-Table~\ref{formats} shows the eight compressed instruction
+Table~\ref{rvc-formats} shows the nine compressed instruction
 formats. CR, CI, and CSS can use any of the 32 RVI registers, but CIW,
-CL, CS, and CB are limited to just 8 of them. Table~\ref{registers}
+CL, CS, CA, and CB are limited to just 8 of them. Table~\ref{registers}
 lists these popular registers, which correspond to registers {\tt x8}
 to {\tt x15}.  Note that there is a
 separate version of load and store instructions that use the stack
@@ -306,6 +306,14 @@ CS & Store &
 \multicolumn{2}{c|}{op} \\
 \cline{3-18}
 
+CA & Arithmetic &
+\multicolumn{6}{|c|}{funct6} &
+\multicolumn{3}{c|}{rd$'$/rs1$'$} &
+\multicolumn{2}{c|}{funct} &
+\multicolumn{3}{c|}{rs2$'$} &
+\multicolumn{2}{c|}{op} \\
+\cline{3-18}
+
 CB & Branch &
 \multicolumn{3}{|c|}{funct3} &
 \multicolumn{3}{c|}{offset} &
@@ -325,7 +333,7 @@ CJ & Jump &
 \end{small}
 }
 \caption{Compressed 16-bit RVC instruction formats.}
-\label{formats}
+\label{rvc-formats}
 \end{table}
 
 
@@ -343,7 +351,7 @@ Floating-Point Register ABI Name    & {\tt fs0}  &  {\tt fs1} &  {\tt fa0} &  {\
 \end{tabular}
 \end{center}
 }
-\caption{Registers specified by the three-bit {\em rs1$'$}, {\em rs2$'$}, and {\em rd$'$} fields of the CIW, CL, CS, and CB formats.}
+\caption{Registers specified by the three-bit {\em rs1$'$}, {\em rs2$'$}, and {\em rd$'$} fields of the CIW, CL, CS, CA, and CB formats.}
 \label{registers}
 \end{table}
 
@@ -492,7 +500,7 @@ following drawbacks to these instructions:
       other instructions can be scheduled around the load and store
       multiple instructions, leading to a potential performance loss.
 \item The desire for sequential register allocation might conflict with
-      the featured registers selected for the CIW, CL, CS, and CB formats.
+      the featured registers selected for the CIW, CL, CS, CA, and CB formats.
 \end{itemize}
 Furthermore, much of the gains can be realized in software by replacing
 prologue and epilogue code with subroutine calls to common
@@ -1007,7 +1015,7 @@ C.SUBW & dest & C.SUBW & src & C1 \\
 \end{tabular}
 \end{center}
 
-These instructions use the CS format.
+These instructions use the CA format.
 
 C.AND computes the bitwise AND of the values in registers {\em rd$'$}
 and {\em rs2$'$}, then writes the result to register {\em rd$'$}.