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| author | Sudharsan Veeravalli <quic_svs@quicinc.com> | 2024-11-29 10:26:00 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-11-29 10:26:00 +0530 |
| commit | 8fcbba82d6c8038c4a0c5859275523414107b198 (patch) | |
| tree | 5ece81426967825d52fa5a563df19599bba4afee /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | d83148f9b9debde1358f0686594da208ce33182e (diff) | |
| download | llvm-8fcbba82d6c8038c4a0c5859275523414107b198.zip llvm-8fcbba82d6c8038c4a0c5859275523414107b198.tar.gz llvm-8fcbba82d6c8038c4a0c5859275523414107b198.tar.bz2 | |
[RISCV] Add Qualcomm uC Xqcisls (Scaled Load Store) extension (#117987)
This extension adds 8 load/store instructions with a scaled index
addressing mode.
The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest
This patch adds assembler only support.
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index e4f7ee3..95658f2 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -684,6 +684,8 @@ DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size, "CORE-V Immediate Branching custom opcode table"); TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcicsr, DecoderTableXqcicsr32, "Qualcomm uC CSR custom opcode table"); + TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcisls, DecoderTableXqcisls32, + "Qualcomm uC Scaled Load Store custom opcode table"); TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table"); return MCDisassembler::Fail; |