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| author | Sudharsan Veeravalli <quic_svs@quicinc.com> | 2024-11-28 12:46:15 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-11-28 12:46:15 +0530 |
| commit | c4645ffedacad18e4cd1dd372288aa55178b1c44 (patch) | |
| tree | c498fc477687e92f8069fb208882dd22f56a8b3f /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | 9ea5be639d31560faec993b4aebb3e10c7d4c8e2 (diff) | |
| download | llvm-c4645ffedacad18e4cd1dd372288aa55178b1c44.zip llvm-c4645ffedacad18e4cd1dd372288aa55178b1c44.tar.gz llvm-c4645ffedacad18e4cd1dd372288aa55178b1c44.tar.bz2 | |
[RISCV] Add Qualcomm uC Xqcicsr (CSR) extension (#117169)
The Qualcomm uC Xqcicsr extension adds 2 instructions that can read and
write CSRs.
The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest
This patch adds assembler only support.
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index cf8e337..e4f7ee3 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -682,6 +682,8 @@ DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size, "CORE-V SIMD extensions custom opcode table"); TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbi, DecoderTableXCVbi32, "CORE-V Immediate Branching custom opcode table"); + TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcicsr, DecoderTableXqcicsr32, + "Qualcomm uC CSR custom opcode table"); TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table"); return MCDisassembler::Fail; |