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| author | Sudharsan Veeravalli <quic_svs@quicinc.com> | 2024-12-14 00:06:58 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-12-14 00:06:58 +0530 |
| commit | 668d9688ac8aa97d9156cecabd25bf2a8e82bc9d (patch) | |
| tree | 4de52259d461e8c35be6d8d647e79e3a914c3b20 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | f01b62ad4881e61dc5d84e1faa984917ac43453c (diff) | |
| download | llvm-668d9688ac8aa97d9156cecabd25bf2a8e82bc9d.zip llvm-668d9688ac8aa97d9156cecabd25bf2a8e82bc9d.tar.gz llvm-668d9688ac8aa97d9156cecabd25bf2a8e82bc9d.tar.bz2 | |
[RISCV] Add Qualcomm uC Xqcilsm (Load Store Multiple) extension (#119823)
This extension adds 6 instructions that can do multi-word load/store.
The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest
This patch adds assembler only support.
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index b8ca324..9901719 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -690,6 +690,8 @@ DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size, "Qualcomm uC Arithmetic custom opcode table"); TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcics, DecoderTableXqcics32, "Qualcomm uC Conditional Select custom opcode table"); + TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcilsm, DecoderTableXqcilsm32, + "Qualcomm uC Load Store Multiple custom opcode table"); TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table"); return MCDisassembler::Fail; |