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| author | u4f3 <ricoafoat@gmail.com> | 2025-03-14 02:13:02 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-03-13 11:13:02 -0700 |
| commit | e61859f14ddd4a1c816518676a2a6dc19ef92206 (patch) | |
| tree | f6475c109f68381b1d229959f2b0129a6dd9865a /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | c2b66ce655e5168b15b619386e7197039b74fe26 (diff) | |
| download | llvm-e61859f14ddd4a1c816518676a2a6dc19ef92206.zip llvm-e61859f14ddd4a1c816518676a2a6dc19ef92206.tar.gz llvm-e61859f14ddd4a1c816518676a2a6dc19ef92206.tar.bz2 | |
[RISCV] Add Qualcomm uC Xqcili (load large immediates) extension (#130012)
The Xqcili extension includes a two instructions that load large
immediates than is available with the base RISC-V ISA.
The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.7.0
This patch adds assembler only support.
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 505eb98..f979af4 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -651,8 +651,9 @@ static constexpr FeatureBitset XqciFeatureGroup = { RISCV::FeatureVendorXqcibm, RISCV::FeatureVendorXqcicli, RISCV::FeatureVendorXqcicm, RISCV::FeatureVendorXqcics, RISCV::FeatureVendorXqcicsr, RISCV::FeatureVendorXqciint, - RISCV::FeatureVendorXqcilia, RISCV::FeatureVendorXqcilo, - RISCV::FeatureVendorXqcilsm, RISCV::FeatureVendorXqcisls, + RISCV::FeatureVendorXqcili, RISCV::FeatureVendorXqcilia, + RISCV::FeatureVendorXqcilo, RISCV::FeatureVendorXqcilsm, + RISCV::FeatureVendorXqcisls, }; static constexpr FeatureBitset XSfVectorGroup = { |