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| author | quic_hchandel <165007698+hchandel@users.noreply.github.com> | 2024-12-12 11:12:09 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-12-12 11:12:09 +0530 |
| commit | 0614c601b44ca2f214a9868a8b672ea695d5d56a (patch) | |
| tree | 90fed320bdf95228b5c6d6ef789045f1e59d00f6 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | 088db868f3370ffe01c9750f75732679efecd1fe (diff) | |
| download | llvm-0614c601b44ca2f214a9868a8b672ea695d5d56a.zip llvm-0614c601b44ca2f214a9868a8b672ea695d5d56a.tar.gz llvm-0614c601b44ca2f214a9868a8b672ea695d5d56a.tar.bz2 | |
[RISCV] Add Qualcomm uC Xqcics(Conditional Select) extension (#119504)
The Qualcomm uC Xqcics extension adds 8 conditional select instructions.
The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest
This patch adds assembler only support.
---------
Co-authored-by: Harsh Chandel <hchandel@qti.qualcomm.com>
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 4d56304..b8ca324 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -688,6 +688,8 @@ DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size, "Qualcomm uC Scaled Load Store custom opcode table"); TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcia, DecoderTableXqcia32, "Qualcomm uC Arithmetic custom opcode table"); + TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcics, DecoderTableXqcics32, + "Qualcomm uC Conditional Select custom opcode table"); TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table"); return MCDisassembler::Fail; |