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| author | Brandon Wu <brandon.wu@sifive.com> | 2023-11-03 10:52:37 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-11-03 10:52:37 +0800 |
| commit | 74f38df1d1361f77fab56f6e647ebf37972faf7c (patch) | |
| tree | 39b46063d91457e164c5de9249c4c7487b63f7bf /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | 945d2e6e603dd9cc5d155a3a34b67ecf17b91b68 (diff) | |
| download | llvm-74f38df1d1361f77fab56f6e647ebf37972faf7c.zip llvm-74f38df1d1361f77fab56f6e647ebf37972faf7c.tar.gz llvm-74f38df1d1361f77fab56f6e647ebf37972faf7c.tar.bz2 | |
[RISCV] Support Xsfvfnrclipxfqf extensions (#68297)
FP32-to-int8 Ranged Clip Instructions
https://sifive.cdn.prismic.io/sifive/0aacff47-f530-43dc-8446-5caa2260ece0_xsfvfnrclipxfqf-spec.pdf
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index fd9e278..f3a4945 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -553,6 +553,9 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size, TRY_TO_DECODE_FEATURE( RISCV::FeatureVendorXSfvfwmaccqqq, DecoderTableXSfvfwmaccqqq32, "SiFive Matrix Multiplication Instruction opcode table"); + TRY_TO_DECODE_FEATURE( + RISCV::FeatureVendorXSfvfnrclipxfqf, DecoderTableXSfvfnrclipxfqf32, + "SiFive FP32-to-int8 Ranged Clip Instructions opcode table"); TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfcie, DecoderTableXSfcie32, "Sifive CIE custom opcode table"); TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbitmanip, |