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| author | quic_hchandel <quic_hchandel@quicinc.com> | 2025-03-18 15:18:43 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-03-18 15:18:43 +0530 |
| commit | 036c6cb37c5647017f98291b3ecd6fb5a2ee2cf4 (patch) | |
| tree | 806f1ebed241808dfd3b0acc800cf0cd73d9adfd /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | 194eceff4327912e6f9167478262961d50516750 (diff) | |
| download | llvm-036c6cb37c5647017f98291b3ecd6fb5a2ee2cf4.zip llvm-036c6cb37c5647017f98291b3ecd6fb5a2ee2cf4.tar.gz llvm-036c6cb37c5647017f98291b3ecd6fb5a2ee2cf4.tar.bz2 | |
[RISCV] Add Qualcomm uC Xqcibi (Branch Immediate) extension (#130779)
This extension adds twelve conditional branch instructions that use an
immediate operand for the source.
The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.7.0
This patch adds assembler only support.
Co-authored-by: Sudharsan Veeravalli <quic_svs@quicinc.com>
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 081101f..a5d4101 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -648,12 +648,12 @@ static constexpr FeatureBitset XRivosFeatureGroup = { static constexpr FeatureBitset XqciFeatureGroup = { RISCV::FeatureVendorXqcia, RISCV::FeatureVendorXqciac, - RISCV::FeatureVendorXqcibm, RISCV::FeatureVendorXqcicli, - RISCV::FeatureVendorXqcicm, RISCV::FeatureVendorXqcics, - RISCV::FeatureVendorXqcicsr, RISCV::FeatureVendorXqciint, - RISCV::FeatureVendorXqcili, RISCV::FeatureVendorXqcilia, - RISCV::FeatureVendorXqcilo, RISCV::FeatureVendorXqcilsm, - RISCV::FeatureVendorXqcisls, + RISCV::FeatureVendorXqcibi, RISCV::FeatureVendorXqcibm, + RISCV::FeatureVendorXqcicli, RISCV::FeatureVendorXqcicm, + RISCV::FeatureVendorXqcics, RISCV::FeatureVendorXqcicsr, + RISCV::FeatureVendorXqciint, RISCV::FeatureVendorXqcili, + RISCV::FeatureVendorXqcilia, RISCV::FeatureVendorXqcilo, + RISCV::FeatureVendorXqcilsm, RISCV::FeatureVendorXqcisls, }; static constexpr FeatureBitset XSfVectorGroup = { |