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| author | Djordje Todorovic <djordje.todorovic@htecgroup.com> | 2025-01-28 08:04:09 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-01-28 08:04:09 +0100 |
| commit | 0cb7636a462a8d4209e2b6344304eb43f02853eb (patch) | |
| tree | e2b9f89cfc1e2091054c470e070ae8632c54d0fd /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | b968fd95026639a2a1d2057627b41622f3b5c97d (diff) | |
| download | llvm-0cb7636a462a8d4209e2b6344304eb43f02853eb.zip llvm-0cb7636a462a8d4209e2b6344304eb43f02853eb.tar.gz llvm-0cb7636a462a8d4209e2b6344304eb43f02853eb.tar.bz2 | |
[RISCV] Add MIPS extensions (#121394)
Adding two extensions for MIPS p8700 CPU:
1. cmove (conditional move)
2. lsp (load/store pair)
The official product page here:
https://mips.com/products/hardware/p8700
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 1c4f322..3ec4658 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -681,6 +681,11 @@ DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size, "SiFive sf.cflush.d.l1 custom opcode table"); TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfcease, DecoderTableXSfcease32, "SiFive sf.cease custom opcode table"); + TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXMIPSLSP, DecoderTableXmipslsp32, + "MIPS mips.lsp custom opcode table"); + TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXMIPSCMove, + DecoderTableXmipscmove32, + "MIPS mips.ccmov custom opcode table"); TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbitmanip, DecoderTableXCVbitmanip32, "CORE-V Bit Manipulation custom opcode table"); |