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| author | Sudharsan Veeravalli <quic_svs@quicinc.com> | 2025-01-03 06:33:27 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-01-03 06:33:27 +0530 |
| commit | 532a2691bc015fafdd356c10b17c466fe28c49b1 (patch) | |
| tree | 241d46998db8a7d5ea2b52268de0e7f27a87981a /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | 6dcd2b035da34fa53693b401139a419adb7342db (diff) | |
| download | llvm-532a2691bc015fafdd356c10b17c466fe28c49b1.zip llvm-532a2691bc015fafdd356c10b17c466fe28c49b1.tar.gz llvm-532a2691bc015fafdd356c10b17c466fe28c49b1.tar.bz2 | |
[RISCV] Add Qualcomm uC Xqcicli (Conditional Load Immediate) extension (#121292)
This extension adds 12 instructions that conditionally load an immediate
value.
The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest
This patch adds assembler only support.
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 57443d3..3012283 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -695,6 +695,9 @@ DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size, TRY_TO_DECODE_FEATURE( RISCV::FeatureVendorXqciac, DecoderTableXqciac32, "Qualcomm uC Load-Store Address Calculation custom opcode table"); + TRY_TO_DECODE_FEATURE( + RISCV::FeatureVendorXqcicli, DecoderTableXqcicli32, + "Qualcomm uC Conditional Load Immediate custom opcode table"); TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table"); return MCDisassembler::Fail; |