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| author | Sudharsan Veeravalli <quic_svs@quicinc.com> | 2024-12-01 17:06:22 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-12-01 17:06:22 +0530 |
| commit | 6881c6d2a6ef2b9f1736afb124b2486d6b8bc603 (patch) | |
| tree | 2780ad92fcd14056abf3bba980072c72d94d6b8d /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | 017c75bfacdfa25594f8212a427627cff7aa98f3 (diff) | |
| download | llvm-6881c6d2a6ef2b9f1736afb124b2486d6b8bc603.zip llvm-6881c6d2a6ef2b9f1736afb124b2486d6b8bc603.tar.gz llvm-6881c6d2a6ef2b9f1736afb124b2486d6b8bc603.tar.bz2 | |
[RISCV] Add Qualcomm uC Xqcia (Arithmetic) extension (#118113)
This extension adds 11 instructions that perform integer arithmetic.
The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest
This patch adds assembler only support.
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 95658f2..4d56304 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -686,6 +686,8 @@ DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size, "Qualcomm uC CSR custom opcode table"); TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcisls, DecoderTableXqcisls32, "Qualcomm uC Scaled Load Store custom opcode table"); + TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcia, DecoderTableXqcia32, + "Qualcomm uC Arithmetic custom opcode table"); TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table"); return MCDisassembler::Fail; |